THE Analog Thing — Volume 4 — Programming

About This Volume

Volumes 1 through 3 of this series establish hardware architecture, the computing elements, and the electrical specification of THE Analog Thing (THAT). Volume 4 is the programmer’s manual: it explains how to translate a mathematical description of a dynamic system into a working patch on THAT’s front panel, how to keep all signals within the ±10 V machine unit, and how to observe and interpret results. Volume 5 covers multi-unit Master/Minion chains; Volume 6 covers hybrid digital/analog interfacing via the HYBRID port.

Scope — All element counts, voltage levels, and mode labels in this volume are verified against the THAT v1.3 schematics (Analog Paradigm, 2022) and the First Steps guide v2.0 (Fischer & Ulmann, 2023). No values have been inferred or extrapolated from outside sources.

The machine unit and its physical voltage

THAT represents every problem quantity as a voltage in the closed interval −10 V to +10 V. The programmer never works directly with volts; instead, the machine unit (MU) is defined as ±1, where +1 corresponds to +10 V and −1 corresponds to −10 V. The translation is exact and linear:

$$V = 10 \times u, \qquad u \in [-1,;+1]$$

A DC/DC converter on the Base PCB steps the 5 V USB-C supply up to a regulated ±12 V rail; the ±10 V machine unit is derived from that rail, leaving a 2 V headroom before the op-amps saturate and the OL (overload) LED illuminates. The overload comparator trips at approximately ±10 V; any signal that exceeds ±1 MU clips and the corresponding output is unusable.

Element inventory

The table below is the authoritative resource count for a single THAT v1.3 unit, read from the Front PCB schematic (THAT-Front_v1.3_01/02.png).

Table 1 — Computing element inventory, THAT v1.3 (single unit)

Each integrator provides five input jacks: three weighted ×1 (white circles) and two weighted ×10 (black circles), plus an IC (initial condition) jack and a SLOW jack. Each summer provides seven input jacks: four weighted ×1 and three weighted ×10. Each integrator and each summer exposes a Summing Junction (SJ) jack so that a resistor network (XIR) can augment the input count. Inverters expose one input jack and two output jacks (stacked for fanout). Multipliers expose two input jacks and two output jacks.

The Method — Turning an ODE into a Patch

Analog computer programming rests on a single insight: a chain of integrators driven by a feedback signal continuously satisfies the differential equation it was derived from. The standard workflow is known as the Kelvin feedback technique.

Step 1 — Write the equation in standard form

Isolate the highest derivative on the left-hand side. For an nth-order ODE the left side reads x⁽ⁿ⁾ and the right side is a function of lower derivatives and independent variables:

x'' = f(x', x, t)

For a second-order equation this gives x” on the left. If x” is assumed to be available as a voltage at an output jack, everything on the right-hand side can be formed by combining that signal with weighted copies of itself integrated once and twice.

Step 2 — Draw the integrator chain

Each integration step:

• produces the next lower derivative at its output jack, and
• inverts sign (integrators on THAT are inverting; this is the standard op-amp topology).

For x” → x’ → x the patch uses two integrators in series:

                 ┌──────────────────────────────────────┐
                 │             feedback                  │
                 ▼                                       │
  (assumed x'')──[INT1]──(−x')──[INT2]──(x)─────────────┤
                   │                     │              │
                  −x'                    x          (to adder)

Because INT1 inverts, its output is −x’. Because INT2 inverts −x’, its output is +x. The sign tracking must be done explicitly at every node.

Step 3 — Form the right-hand side

The right-hand side of the ODE is assembled from summers, inverters, multipliers, and coefficient potentiometers fed by taps from the integrator chain. The output of this network must equal the assumed x” — this closes the feedback loop. If the signs do not match, add an inverter.

Step 4 — Set initial conditions

Each integrator holds an initial-condition voltage on its IC jack. In IC mode (mode selector to IC), the integrator output is driven to −IC_input (inverted). Setting IC = −x₀ therefore yields output = +x₀ at t=0 when OP begins. IC jacks accept any signal in the ±1 MU range, including outputs of coefficient potentiometers set to the desired starting value.

Step 5 — Verify sign conventions at every node

A sign error is the most common patching mistake. The recommended practice is to annotate each wire in the patch diagram with its sign relative to the highest derivative. THAT provides both output jacks of integrators and summers; the second jack is a duplicate for fanout — both carry the same polarity.

Signal-flow example: first-order decay

The simplest closed patch: one integrator, one coefficient potentiometer.

   ┌─────────────────────────────────────────┐
   │                  λ                       │
   │   +1 ──[POT1]──× ──────────────────────►│
   │                                          │
   │          ┌──────────────────────────┐    │
   └──────────► INT1  (SLOW connected)   ├────┘
              │  IC: −N₀                 │
              └──────────┬───────────────┘
                         │ output = +N(t)
                         ▼
                     [INV1] ──► display

The differential equation modelled is dN/dt = −λN. The integrator inverts, so feeding its output back to its own input (via a potentiometer for λ) implements negative-feedback decay. An inverter after the integrator recovers the positive display variable N(t).

Magnitude Scaling on a ±10 V Machine

Why overload matters

When any node voltage exceeds ±10 V the associated op-amp saturates. The OL LED illuminates and the offending integrator or summer locks its output at the rail. Because integrators in feedback loops drive each other, a single overload cascades through the patch within microseconds, destroying all computed signals. The machine unit headroom — 2 V above ±10 V before the ±12 V rail — is not usable signal range; it is a safety margin only.

Rule — Design so that the maximum excursion of every node stays below |0.9 MU| in normal operation. Leaving 10 % headroom accommodates parameter excursions during interactive tuning.

Magnitude scaling procedure

Let the raw problem variable be Q with physical peak value Q_max. Define the scaled machine variable:

$$u_Q = \frac{Q}{Q_{\max}}$$

so that |u_Q| ≤ 1. Every coefficient involving Q must be adjusted by the same factor so that the equations remain consistent.

Scaling table — mass-spring-damper example

The raw equation is my” + Dy’ + sy = 0, resolved as:

$$y” = \frac{1}{m}\left(-Dy’ - sy\right)$$

Estimated physical peaks: y_max = A (displacement), y’_max = ωA (velocity), y”_max = ω²A (acceleration). Define u_y = y/A, u_v = y’/(ωA), u_a = y”/(ω²A).

After substitution, the coefficients in the scaled equation become D/(mω) and s/(mω²). Both must fall in (0,1] for the coefficient potentiometers to implement them directly. If a computed coefficient exceeds 1, use the ×10 weighted inputs (black circles) to provide an implicit factor of ten, reducing the required pot setting by ×0.1.

Using the ×10 weighted inputs for implicit gain

Every integrator and summer input marked with a black circle multiplies the incoming signal by 10 before presenting it to the summing junction. This is not a separate element; it is a built-in resistor ratio. Connecting a signal carrying value u to a ×10 input and setting the coefficient potentiometer to α delivers an effective gain of 10α — useful when the scaled coefficient is between 1 and 10 and re-scaling the problem variable is inconvenient.

Table 2 — Input weighting on integrators and summers

Scaling tree diagram

The diagram below illustrates how a second-order system with three nodes maps its peak excursions into the machine unit interval. Widths represent voltage headroom; each bar must fit within ±1 MU.

  MU ─────────────────────────────────────────────── +1.0
  0.9 ─────────────────────────────────────          ← design ceiling
          ██████████████████████████  u_a  peak ≈ 0.85
          ████████████████            u_v  peak ≈ 0.60
          ████████████████████████    u_y  peak ≈ 0.75
  0.0 ──────────────────────────────────────────────  0
         (mirrored below zero line by symmetry)
  −1.0 ─────────────────────────────────────────── −1.0

Figure 1 — Magnitude scaling target: all nodes inside ±0.9 MU

If any node peak exceeds 0.9 MU, divide that problem variable by a larger scale factor (or equivalently reduce the corresponding coefficient).

Overload indicators and diagnosis

THAT provides three State LEDs: OP (green — patch running), IC (yellow — initial condition phase), OL (red — overload active). When OL illuminates during a patch run:

1. Switch to HALT mode immediately to freeze the outputs.
2. Connect the panel meter to each node in turn (via the U output jack) to locate the offending signal.
3. Reduce the scale factor of the overloading variable by 2× and re-derive affected coefficients.

Tip — The panel meter reads ±1 MU in IC, OP, and HALT modes when the U output jack is patched. In COEFF mode it reads the selected potentiometer value in the range 0 to 1.

Time Scaling and the Time-Constant Switches

The integrator time constant

An unmodified THAT integrator with a ×1 input connected to −1 MU and IC = 0 reaches +1 MU output in exactly 1 ms (from the First Steps manual, Section 8). This defines the base time constant τ = 1 ms per machine unit of input.

Equivalently: the integrator integrates at a rate of 1 MU/ms when driven by a 1 MU input signal. For a sinusoid at angular frequency ω (rad/ms) the integrator introduces a gain of 1/ω and a 90° phase lag — the standard op-amp integrator characteristic.

SLOW mode — reducing speed by 100×

Connecting an integrator’s output jack back to its own SLOW jack (a dedicated input jack on each integrator) introduces an additional RC time constant that extends the integration time to 100 ms per machine unit, a factor of 100 slowdown. This is implemented entirely by a passive resistor/capacitor network accessed through the SLOW jack; no mode switch is required.

Table 3 — THAT integrator speed modes (verified from First Steps v2.0 §8)

Each integrator can independently have its SLOW jack connected or left open. Mixed-speed patches — some integrators fast, others slow — are legitimate and are used in the neuronal bursting example (Section 9.4 of First Steps), where the slow ion-channel integrator runs 100× more slowly than the two fast integrators.

The mode selector and repetitive operation

Time scaling at the patch level is complemented by the OP-Time potentiometer and the REP/REPF mode selector positions, which control how long each OP interval lasts between automatic IC resets.

Table 4 — Mode selector positions and OP-time ranges

In REP and REPF modes, THAT automatically alternates between a brief IC phase (to reload initial conditions) and the OP phase (to run the patch). The Trigger Out RCA jack on the rear panel emits a synchronisation pulse at the start of each OP phase, enabling oscilloscope external triggering for flicker-free displays.

Tip — For phase-plane (X-Y) displays, REPF at 80 ms OP time typically yields a flicker-free Lissajous figure on most digital oscilloscopes. Increase OP time if the trajectory appears truncated before it closes.

Time scaling by coefficient selection

For phenomena whose natural time scale differs from THAT’s 1 ms base constant, the problem can be re-scaled in time by the factor k_t. If the natural period is T_natural and the desired patch period is T_patch:

$$k_t = \frac{T_{\text{patch}}}{T_{\text{natural}}}$$

Every velocity and rate coefficient in the scaled ODE is multiplied by k_t. For example, a chemical reaction with τ_natural = 1 s mapped to T_patch = 10 ms uses k_t = 0.01; all time-derivative coefficients shrink by 0.01, which is easily achievable with the coefficient potentiometers without needing the SLOW jacks. Conversely, a multi-decade orbital simulation compressed to 100 ms uses a large k_t and may require the ×10 inputs to implement the inflated coefficients.

   Time scaling relationship:

   T_natural   |  k_t   | Technique
   ────────────|────────|─────────────────────────────────────────
   ~1 ms       | 1.0    | Use integrators at normal speed
   ~100 ms     | 0.01   | Normal speed, reduce all coefficients ×0.01
   ~1 s        | 0.001  | Normal speed or SLOW mode on all integrators
   ~10 s       | 0.0001 | SLOW mode (×0.01) + coefficient reduction ×0.01
   ~1 ms fast  | 100    | REPF mode; scale coefficients ×100 with ×10 inputs

Table 5 — Time scaling strategies

Setting Coefficients

The eight coefficient potentiometers

COEFF1 through COEFF8 are single-turn potentiometers with a graduated (not numbered) dial, adjustable from 0 to 1. Each potentiometer has an input jack and an output jack on the patch panel. The procedure for setting a specific value:

1. Connect the potentiometer’s input jack to the +1 machine unit jack.
2. Switch THAT to COEFF mode.
3. Rotate the Coefficient Selector knob to the desired potentiometer number (1–8).
4. The Panel Meter displays the current output in the range 0 to 1.
5. Adjust the potentiometer knob until the meter reads the target value.
6. Return THAT to IC or OP mode when all potentiometers are set.

Note — The coefficient selector and panel meter display only one potentiometer at a time. Set all required potentiometers before leaving COEFF mode, then switch to IC to verify initial conditions.

The output of each potentiometer (connected as a voltage divider between the input signal and ground) feeds one or more computing element inputs. The potentiometer output jack is an output — do not connect multiple signal sources to it.

Negative coefficients

Coefficient potentiometers are unipolar: they output values in [0, +1] of their input. To implement a negative coefficient −α, connect the potentiometer input to the −1 machine unit jack instead of +1. The output is then −α, suitable for direct connection to a ×1 input jack of an integrator or summer.

Alternatively, connect the potentiometer output to a ×1 input of an inverter and use the inverter output; this preserves the flexibility to change sign by re-patching the potentiometer input between +1 and −1.

The adjustable ±1 helper circuit

Section 10.4 of First Steps documents a helper circuit (using a comparator) that extends the single potentiometer range from [0,1] to [−1,+1]. This is used in the polynomial generator example (Section 9.9) so that coefficients a, b, c, d can each be swept across the full machine unit range interactively.

Coefficient summary table

Table 6 — Coefficient potentiometer ranges by connection method

Stacking outputs for multiple destinations

A coefficient potentiometer output (like any output jack on THAT) can drive multiple destinations by physically stacking banana plugs into the same jack. There is no limit specified in the documentation, but practical stacking depth is 2–3 plugs before mechanical reliability decreases. For wider fanout, route through an inverter pair (to restore sign) or use the duplicate output jacks provided on each integrator and summer.

Resistor networks for extended input count

When an integrator or summer requires more inputs than its native jacks provide, a resistor network (XIR) can be connected via the SJ (summing junction) jacks. Both the computing element and the XIR expose an SJ jack; connecting these two SJ jacks together merges the resistor networks at the virtual ground of the op-amp input. Each XIR provides additional ×1 and ×10 input jacks. THAT includes two XIR units (XIR1, XIR2).

Note — The SJ jack is a true summing junction (virtual ground node), not an output. Do not connect an SJ jack to any output jack; doing so will force the virtual ground potential to a non-zero value, degrading accuracy across the entire element.

Reading Results — Display, Scope, and X-Y

The panel meter

THAT’s built-in panel meter (a 3½-digit LCD) serves two purposes depending on mode:

Table 7 — Panel meter display modes

In OP mode, the meter provides a slow-update numerical read of whatever is patched to the U output jack on the front panel. This is ideal for monitoring DC or slowly-varying signals (population levels, fuel quantity in the lunar lander example) but it is too slow for signals varying faster than a few hertz.

The four output jacks (X, Y, Z, U)

The front panel carries four labelled output jacks: X, Y, Z, U. Patching any signal to one of these jacks routes that signal to both:

• the corresponding RCA Out jack on the rear panel, attenuated to ±1 V range (audio-compatible); and
• the HYBRID port on the rear panel, level-shifted to 0–3.3 V (for microcontroller ADC inputs).

The X, Y, Z, U jacks are inputs on the front panel (accepting a patch cable from any computed signal) and outputs on the rear panel. Do not confuse the two.

Oscilloscope connection

Connect the rear-panel RCA Out X (and Y for dual-channel) to the oscilloscope inputs using the included RCA-to-RCA cable and appropriate RCA-to-BNC adapters (not included). THAT’s output is ±1 V at the RCA jacks (10:1 attenuated from the ±10 V front-panel signals). Set oscilloscope input sensitivity to ≈ 200 mV/div for full-scale visibility.

THAT supports oscilloscope frequencies up to 200 kHz (from the First Steps requirements section). Software oscilloscopes via audio input interfaces work down to approximately 20 kHz — adequate for most patch problems but note that audio interfaces insert AC-coupling capacitors that remove DC components, distorting exponential and step signals.

Time-domain display (roll mode)

In REP mode with OP time set to 1–10 seconds, set the oscilloscope to roll mode (continuous sweep without trigger). The patch runs in real time; the user can adjust coefficients by rotating the potentiometer knobs and observe the waveform shift immediately.

Phase-plane (X-Y) display

The most informative display for two-dimensional autonomous systems (predator-prey, Lorenz, Euler spiral) is the X-Y mode, which plots one state variable against another rather than against time.

1. Patch the first state variable to OUT X.
2. Patch the second state variable to OUT Y.
3. Set the oscilloscope to X-Y mode.
4. Run THAT in REPF mode at an OP time that traces the trajectory in 30–100 ms for flicker-free rendering.

The Trigger Out RCA jack provides a rising-edge pulse at the start of each OP interval; connect this to the oscilloscope’s external trigger if the display appears to drift or rotate.

Signal monitoring table

Table 8 — Recommended display methods by signal type

Photo reference — THAT panel

Figure 2 — THAT v1.3 front panel. The coefficient potentiometers (COEFF1–8) occupy the right strip; mode selector, OP-time pot, and coefficient selector are at lower right. Integrators INT1–INT5 run across the upper left; summers SUM1–SUM4 occupy the middle band. Output jacks X, Y, Z, U are visible at upper right.

Full Worked Example — Damped Harmonic Oscillator

This section demonstrates the complete programming workflow: equation → patch diagram → magnitude scaling → time scaling → coefficient setting → display. The system chosen — a damped harmonic oscillator — is fundamental to mechanics, acoustics, and electronics, and it exercises two integrators, one summer, two coefficient potentiometers, and the comparator (optionally, for detecting zero-crossings).

Physical system

A mass m on a spring with stiffness s and viscous damping coefficient D, displaced from equilibrium:

$$m\ddot{y} + D\dot{y} + sy = 0$$

Dividing by m and isolating the highest derivative:

$$\ddot{y} = -\frac{D}{m}\dot{y} - \frac{s}{m}y$$

Define for brevity: α = D/m, β = s/m.

$$\ddot{y} = -\alpha\dot{y} - \beta y$$

Characteristic angular frequency ω₀ = √β, damping ratio ζ = α/(2ω₀).

Representative numerical values (from the First Steps mass-spring-damper example):

• s = 0.5 (spring coefficient, pot 2)
• D = 0.05 (damping coefficient, pot 3)
• 1/m = 0.5 (inverse mass, pot 4)
• y₀ = 0.5 (initial displacement, pot 1)

Step 1 — Magnitude scaling

Identify peak excursions. For underdamped motion, y oscillates with amplitude ≈ y₀ at start. Velocity peak ≈ ω₀ × y₀. With β = s/m = 0.5 × 0.5 = 0.25, ω₀ = 0.5 rad/ms. At y₀ = 0.5 MU, velocity peak ≈ 0.25 MU. Both are well within ±1 MU — no additional scaling is needed for these values. Acceleration peak ≈ β × y₀ = 0.125 MU. All nodes are comfortably below the 0.9 MU design ceiling.

Step 2 — Time scaling

The natural period is T = 2π/ω₀ = 2π/0.5 ≈ 12.6 ms. In REPF mode at 80 ms OP time, the patch traces approximately six full oscillation cycles — adequate for observing the decay envelope. No time scaling beyond the coefficient choices is required.

Step 3 — Patch diagram

The signal-flow diagram below shows the complete patch. Sign tracking is annotated at each node.

                          α (COEFF3)      β (COEFF2)
                             │                │
  ┌──────────────────────────┴────────────────┴──────┐
  │                                                   │
  │         SUM1 (×1 inputs)                         │
  │   −ẏ ──────────────────────────►                 │
  │    y ───────────────────────────►  −ÿ ───────────┤
  │                                         │         │
  └─────────────────────────────────────────┘         │
                                                      │
   COEFF1 (y₀) → IC                                   │
   +1 ─[COEFF1]─► IC jack of INT1                    │
                                                      ▼
            ┌────────────────────────────────[SUM1 output]
            │                                         │
           INT1 (fast) ◄── IC = −y₀                  │
            │                                         │
            │  output = +ẏ (inverted of −ẏ)           │
            ▼                                         │
           INT2 (fast) ◄── IC = 0                    │
            │                                         │
            │  output = −y (inverted of +ẏ)           │
            │                                         │
           INV1 ──► y (positive displacement)         │
            │                                         │
            ├──────────────────────────────────────►  │ (via COEFF2 = β)
            │                                         │
            └── to OUT X (display)                    │
                                                      │
  INT1 output (+ẏ) ──[INV2]──► −ẏ ──► SUM1 (via COEFF3 = α)

Figure 3 — Signal-flow patch for damped harmonic oscillator (THAT v1.3)

Patch diagram — SVG format

Damped Harmonic Oscillator — THAT Patch Signal Flow

  Time-domain output (underdamped, ζ ≈ 0.05):

    +1 ┤
  0.5 ┤   ╭──╮        ╭──╮
       ┤  ╭╯  ╰──╮  ╭─╯  ╰──╮
       ┤ ─╯      ╰──╯        ╰────────
  0.0 ┤─────────────────────────────────────► t
       ┤
  −0.5┤
    −1 ┤

  Phase-plane output (spiral converging to origin):

         ẏ
    ┤  ↗ ○ ↘
    ┤ ↑   │  ↓
    ┤ ←   0  →    y
    ┤ ↑   │  ↓
    ┤  ↖ ○ ↙      (spiral inward over successive cycles)