THE Analog Thing — Volume 3 — Computing elements & patching

TRUE path (A+B > 0) FALSE path (A+B ≤ 0)

The comparator introduces a small propagation delay (the switching time of the comparator IC and buffer), but for the continuous-time signals typical of THAT patches this delay is negligible.

Jack Summary

Practical Use

Comparators enable piecewise-linear and switched-parameter patches — the closest THAT gets to conditional logic. Representative applications from the First Steps manual:

• Bouncing ball (section 9.8): a Zener diode in series with comparator action detects when the ball’s y-position crosses zero (the floor) and injects a velocity reversal impulse.
• max(A, B) / min(A, B) helper functions (sections 10.1, 10.2): the comparator routes whichever of two inputs is larger/smaller to the output.
• abs(A) helper function (section 10.3): comparator selects between +A and −A depending on sign.
• Non-negative clamp (section 10.5): comparator routes A when positive, zero otherwise.

Coefficient Potentiometers

Count and Identification

THAT provides eight coefficient potentiometers, labeled PT1 through PT8 (also referred to as COEFF1 through COEFF8 in the base schematic, region COEFF1-8 visible in THAT-Front_v1.3_01.png). The First Steps manual (Section 7, item 17) refers to “Coefficient Potentiometers” and item 23 labels the associated jacks “Coefficients.” Newsletter #4 explicitly references “the eight coefficient potentiometers” during a description of the test procedure.

Each potentiometer is a single-turn wirewound or cermet pot (production hardware uses a smooth, gradual scale rather than the numbered scale of the very first prototypes, a change noted in Newsletter #1).

Electrical Function

Each coefficient potentiometer is a voltage divider. When its input jack is connected to the +1 machine-unit supply, the output jack delivers a continuously adjustable voltage in the range 0 to +1 (0 V to +10 V). The pot’s wiper position controls the fraction.

To obtain a signed coefficient in the range −1 to +1, the adjustable value helper function (section 10.4 of First Steps) is used: it combines +1 and −1 machine-unit supplies with a comparator to produce a pot-controllable output spanning the full bipolar range.

Setting Procedure

1. Connect the desired pot’s input jack to the +1 machine-unit supply.
2. Place the Mode Selector in COEFF mode.
3. Turn the Coefficient Selector knob to select the desired potentiometer (PT1–PT8).
4. Observe the Panel Meter, which reads 0–1 in COEFF mode.
5. Adjust the pot knob until the displayed value matches the desired coefficient.
6. Repeat for each potentiometer used in the patch.

Note — In COEFF mode the integrators are idle. Setting all coefficients before entering IC or OP mode is the standard workflow.

Jack Assignments

(Naming convention from the base PCB schematic THAT-Base_v1.3_02.png, which shows PT1-IN through PT8-IN and corresponding -OUT lines driving the front-panel coefficient section.)

The Coefficient Selector routes one potentiometer output to the Panel Meter at a time; all eight output jacks remain live simultaneously regardless of the selector position.

The Patching System

Figure: THAT v1.3 front panel schematic showing the full jack layout across the patch field. Reading top-to-bottom: integrators (INT1–INT5), summers (SUM1–SUM4), inverters (INV1–INV4), resistor networks (XIR1–2) at upper left; coefficient potentiometers (COEFF1–8) at upper right; multipliers and comparators in the lower base schematic region.

Physical Format: 2 mm Banana Jacks

THAT’s patch field uses 2 mm banana-plug patch cables — a format distinct from the 4 mm banana plugs common in laboratory instruments and from the 3.5 mm mini-jack format of modular synthesizers. The 2 mm format was chosen deliberately: smaller than 4 mm (allowing higher jack density on the panel) and more rugged than spring-clip patchbay formats used on historic Telefunken and EAI analog computers. The cables supplied with THAT are single-wire (one conductor, no shield), which is adequate because the patch signals are low-impedance op-amp outputs with source impedances of tens of ohms driving loads of tens of kilohms.

The patch field uses gold-plated through-holes in an extra-thick PCB rather than conventional socket hardware. This design reduces per-position cost significantly — the First Steps FAQ (section 11) notes that a conventional socket would cost approximately USD 1.00 each, which across 186 positions would add roughly USD 186 to the bill of materials. The through-hole approach means plugs do not fully seat; the contact spring at the midpoint of the plug barrel makes reliable electrical contact at the gold-plated barrel wall. Plugs may be stacked (inserted into the same hole atop each other) to fan a single output to multiple inputs.

Note — The gold-plated through-holes can accumulate conductive contamination from finger contact (skin oils, flux residue). The First Steps FAQ notes that this is the primary cause of integrators running into overload unexpectedly. A gentle clean with isopropyl alcohol on a cotton swab resolves this. Do not use abrasive materials.

Jack Count: 186 Positions

The total number of plug positions on the patch panel is 186, confirmed by the First Steps FAQ: “one of these sockets plus mounting costs about USD 1.00, which would add up significantly for the 186 plug positions on THAT’s patch panel.” This figure encompasses all input jacks, output jacks, IC jacks, SJ jacks, machine-unit jacks, diode jacks, capacitor jacks, and output-selector jacks.

Jack Shape Vocabulary

Signal Direction Rules

These rules must never be violated:

1. One driver per jack: an input jack may receive exactly one patch cable. Connecting two outputs to the same input jack shorts two op-amp output stages together — a fault condition that triggers the overload LED (OL) and may cause thermal damage to the op-amp output stage.
2. Outputs may fan out freely: one output jack may be connected to any number of input jacks by stacking cables or by daisy-chaining through multiple input jacks.
3. No output-to-output connections: the patch panel provides no protection against this; the operator must prevent it.
4. Do not connect +1 to ground: the First Steps FAQ explicitly warns that connecting the +1 machine-unit supply to ground will blank the display (as it causes a short on the ±10 V reference).

Tip — If a node must drive more than two or three destinations and stacking feels unwieldy, route the signal through a spare unity-weight summer input (with all other inputs unpatched) to create a buffered copy. The inverting sign of the summer must then be cancelled by another inverter — or accounted for in the patch algebra.

Patch Field Jack-Type Decision Tree

Given a jack position on the panel — how to identify it:

Is the symbol a TRIANGLE?
  YES → Output jack. May drive any number of inputs (stack cables freely).
  NO  → Is it a CIRCLE?
          YES → White circle with "1"? → Unity-weight input (×1).
                Black circle with "10"? → Ten-weight input (×10).
          NO  → Is it a DIAMOND?
                  Upper half black? → Machine-unit +1 source (+10 V).
                  Lower half black? → Machine-unit −1 source (−10 V).
                  All white?        → IC jack (integrator) or FB jack (summer).
                Is it labeled "SJ"? → Summing Junction extension point.
                Is it labeled "⏚"? → Analog ground reference.

Daisy-Chaining and Fan-Out Table

The +/−10 V Machine-Unit Convention

THAT represents all computed quantities as voltages in the range −10 V to +10 V. This range is called the machine unit, abstractly normalized to −1 to +1. The +10 V and −10 V supply rails are derived from a DC/DC converter that steps the 5 V USB input up to ±12 V, from which precision ±10 V references are generated for the machine-unit jacks on the panel.

All computing elements clip or saturate near ±10 V. The overload LED (OL on the State LED cluster) illuminates when any element output approaches saturation. An overloaded patch produces a distorted, clipped solution; the remedy is quantity scaling — multiplying all state variables by a common factor k < 1 to keep peak values within machine-unit bounds (see Vol 4 for the complete scaling workflow).

The machine-unit abstraction is important for portability of patch diagrams. A patch diagram drawn in normalized ±1 units runs identically on any analog computer that uses the same normalization, regardless of whether the physical implementation uses ±10 V (THAT), ±100 V (Telefunken RA 741), or ±1 V (some modern CMOS designs). This is the analog analogue of instruction-set portability in digital computing.

OL triggers near here OL triggers near here

Color Coding

The 30 patch cables supplied with THAT are provided in multiple colors. No mandatory color assignment is defined by the hardware; color is entirely a user convention. A widely adopted practice in the THAT community:

Note — Color convention is informal. The patch diagrams in the First Steps manual use specific colors (e.g., “the output of the inverter shown in blue in the patching diagram”) for pedagogical clarity, but these are diagram conventions only and do not imply colored jack groups on the hardware.

Panel Overview Diagram

The figure above shows the v1.3 front PCB schematic. Reading left to right, top to bottom:

Panel region map (schematic coordinate order):

┌──────────────────────────────────────────────────────────────┐
│  INTEGRATORS (INT1–INT5)    │  SUMMERS (SUM1–SUM4)           │
│  5 units, each: 3×(×1)      │  4 units, each: 4×(×1)+3×(×10)│
│  + 2×(×10) + IC + SLOW      │  + FB + SJ + ⏚                │
├──────────────────────────────────────────────────────────────┤
│  INVERTERS (INV1–INV4)      │  RESISTOR NETWORKS (XIR1–XIR2) │
│  4 units, each: 2×(×1)      │  2 units, each: 2×(×1) + SJ   │
│  + SJ + OUT×2               │                                │
├──────────────────────────────────────────────────────────────┤
│  MULTIPLIERS (MUL1–MUL2)    │  COMPARATORS (CMP1–CMP2)       │
│  2 units, each: 2 inputs    │  2 units, A+B control + 2 in   │
│  + 2 outputs                │  + 2 outputs                   │
├──────────────────────────────────────────────────────────────┤
│  COEFF POTS (PT1–PT8)       │  MACHINE UNITS (+1/−1)         │
│  8 units, IN + OUT each     │  Multiple +1 and −1 jacks      │
├──────────────────────────────────────────────────────────────┤
│  DIODES / ZENER DIODES      │  CAPACITORS                    │
│  (passive patch elements)   │  (passive patch elements)      │
├──────────────────────────────────────────────────────────────┤
│  OUTPUT JACKS (X, Y, Z, U)  │  MODE SELECTOR / PANEL METER  │
└──────────────────────────────────────────────────────────────┘

Full Element Inventory

Worked Example — First-Order Exponential Decay

This section walks through a complete single-element patch demonstrating every concept introduced above: machine-unit convention, coefficient setting, integrator wiring, IC assignment, and mode sequencing.

Problem Statement

Radioactive decay follows the first-order ODE:

$$\dot{N} = -\lambda N, \quad N(0) = N_0$$

with solution N(t) = N₀ e^{−λt}. THAT solves this by implementing the integrator equation that defines N directly.

Patch Development

Rearranging for the integrator input:

$$N = -\int \dot{N}, dt = -\int (-\lambda N), dt = \int \lambda N, dt$$

The integrator’s implicit sign inversion is used to advantage: the integrator computes −∫(input)dt, so feeding −λN to the input yields +λN·(−1)·(−1) = +λN at the output — which is N itself, closing the feedback loop correctly.

Step-by-step patch:

1. Set coefficient PT1 to λ (a value between 0 and 1): connect PT1-IN to +1 machine unit, enter COEFF mode, select PT1, adjust to desired λ.
2. Wire the feedback loop: patch INT1-Out1 → PT1-IN. (Wait — PT1-IN is already used. The correct approach: patch INT1-Out1 to a unity input of INT1 itself after routing through PT1.)

Revised signal flow (standard approach from First Steps section 9.1):

Signal-flow diagram — Radioactive Decay:

  +1 ─────────────────►[PT1: λ]──────────────────────────────┐
                            │ (λ, 0 to 1)                     │
                            ▼                                  │
  IC = −N₀ ──────────►[INT1]──────────────────►  N(t)        │
  (applied to IC jack)   │ (×1 input)           (INT1-Out1)   │
                         │                           │         │
                         └───────────────────────────┘         │
                         (INT1-Out1 feeds INT1 ×1 input)       │
                                                               ▼
                                                         [Inverter INV1]
                                                               │
                                                               ▼
                                                         display on scope

Corrected canonical patch (as shown in First Steps fig. 9.1):

• INT1-Out1 → PT1-IN (provides λ·N to the coefficient pot output)
• PT1-OUT → INT1 ×1 input (feeds −λN into integrator, implicit inversion handles sign)
• IC jack on INT1 → −1 machine unit jack (sets N₀ = +1 at t=0, since IC inversion: output = −(−1) = +1)
• INT1-Out1 → INV1 input (inverts to produce positive-valued N for display)
• INV1-Out1 → OUT X jack (routes to oscilloscope or RCA output)

Detailed signal-flow (canonical):

  −1 (machine unit) ────────────────────────────────► IC jack (INT1)
                                                       (sets N(0) = +1)

  INT1-Out1 ─────────────────────────────────────────► INV1 input
                │                                      (for display)
                └──► PT1-IN
                          │
                      PT1-OUT (= λ · N)
                          │
                          ▼
                     INT1 ×1 input
                     (integrates −λN, giving N)

  INV1-Out1 ──────────────────────────────────────────► OUT X

Jack Connection Table

Mode Sequence

1. COEFF: Set PT1 to desired λ (e.g., 0.3 → N(t) = e^{−0.3t}).
2. IC: Integrator output driven to −(−1) = +1 (N₀ = 1 machine unit).
3. OP: Integration begins; observe decaying exponential on oscilloscope.
4. REP (optional): Set OP-Time Potentiometer to 2–3 seconds; THAT auto-cycles IC→OP for a steady oscilloscope trace.

Signal-Flow Diagram (SVG)

Expected Output

Note — Adding a second coefficient potentiometer (PT2) for N₀ allows initial conditions other than ±1. Connect PT2-IN to +1 machine unit, set PT2 to the desired N₀ fraction, then connect PT2-OUT to INT1’s IC jack (replacing the direct −1 connection). Remember the IC inversion: to achieve N(0) = +0.5, the IC jack must receive −0.5, which requires routing PT2 through an inverter or connecting PT2-IN to the −1 supply.

Common Beginner Errors in this Patch

Summary Reference Tables

Quick-Reference: All Computing Elements

Integrator Specifications

Summer Specifications

Multiplier Specifications

Comparator Specifications

Coefficient Potentiometer Specifications

Inverter Specifications

Mode Selector Reference

Newsletter Index for This Volume’s Topics

Patch-Planning Checklist

Before wiring any patch on THAT, the following checklist reduces debugging time:

□  Write the governing ODE(s) in standard form (ẋ = f(x, u, t))
□  Count integrators needed; confirm ≤ 5 (or plan master/minion chain)
□  Assign one integrator per state variable
□  Identify nonlinear (multiplier) terms; confirm ≤ 2 multipliers needed
□  Check for conditional switching; confirm ≤ 2 comparators needed
□  Count coefficient terms; confirm ≤ 8 coefficient pots needed
□  Scale all state variables to ±1 machine unit (see Vol 4)
□  Draw signal-flow diagram with sign at every node
□  Count inversions around each feedback loop (should be odd = negative feedback)
□  Assign cable colors by signal type for visual clarity
□  Set all coefficient pots in COEFF mode before entering IC or OP
□  Verify no output-to-output connections before applying power
□  In OP mode, check OL LED; if lit, re-scale (see Vol 4)

Cross-Reference to Other Volumes