English translation
Dead-Time Element for the Dornier DO 80 Analog Computer
Translation of the original German document: “Totzeitglied” (Dornier, October 1971)
Foreword
The following engineering report was produced after a ten-week period of work at the firm Dornier in Friedrichshafen. The author wishes to express heartfelt thanks to Mr. Becker and Mr. H. Thomas for their exemplary supervision.
Konstanz, October 1971.
Table of Contents
- Mathematical Description of Dead Time — p. 1
- General Operating Principles — p. 2
- Input Operational Amplifier — p. 8
- Analog-to-Digital Converter — p. 14
- Shift Register — p. 19
- Dead Time — p. 22
- Digital-to-Analog Converter — p. 27
- Output Operational Amplifier — p. 31
- Voltage-Controlled Oscillator (VCO) — p. 35
- Control Logic — p. 41
- Operating Modes — p. 45
- Patch Panel — p. 50
- Oscillograms — p. 51
- Technical Data — p. 54
- Overall View of the Dead-Time Element — p. 55
- Complete Control Schematic — p. 55
Dead-Time Element (Totzeitglied)
There exist control-loop elements that possess a comparatively large signal propagation delay, so that a certain time elapses before a change in the input variable begins to make itself felt at the output variable. This time interval is designated “dead time.” Dead time is therefore the time that passes after a change in the manipulated variable before a change in the controlled variable becomes perceptible. Dead time is almost always caused by the finite propagation speed of the command signal within the controlled system. It is therefore also called “transport delay.” Practically occurring dead times range from milliseconds to several minutes.
1. Mathematical Description of Dead Time
The frequency response is obtained from the following consideration. If the input signal is given by x_e = A · e^(jωt), then the time-delayed occurrence of the output signal by the time interval T_t is expressed by:
x_a = A · e^(jω(t – T_t))
This gives: F(jω) = x_a / x_e = e^(–jωT_t)
Dead time has a substantial influence on the controllability of processes and the stability behavior of control loops.
The following dead-time element was developed as an add-on unit for the DO 80 computer. This dead-time element delays the input signal before re-output by a specified dead time. The dead time is adjustable from 1 millisecond up to 10 seconds.
2. General Operating Principles
The general operating principles are explained with the aid of the block diagram (Figure 1).
The dead-time element operates on a sampled-data principle with digital delay or storage of the measured values.
The analog input signal may vary between +10 V and –10 V. The analog-to-digital converter, however, can only process voltages between 0 V and +10 V. The input signal from (–10 V … +10 V) is therefore compressed by the input operational amplifier into the voltage range (0 V … +10 V). This input signal is fed to the analog-to-digital converter (ADC).
An internal clock (Strobe) converts the signal present at the ADC input into an 8-bit digital word. After conversion this 8-bit word is entered into a parallel 1 × 100-bit shift register and becomes the first word in the 100-word shift register. With each subsequent clock pulse this word is shifted one position in the shift register, and at each clock pulse a new input sample is converted into a new 8-bit word and taken up by the shift register. After 100 clock pulses the input values are again available at the output of the shift register in the form of an 8-bit word.
The conversion time of the ADC is 5 microseconds; during this time no pending input sample is processed. The ADC clock (Strobe) period is therefore always greater than 5 µs. The shift register also requires an external clock (Clock) so that it can accept a word and then shift it systematically.
There must be a certain synchronism between the Strobe clock of the ADC and the shift-register clock (Clock), so that the shift register accepts a word only when a corresponding word has been output by the ADC. This process is described in more detail below.
The 8-bit words appearing at the output of the shift register are supplied to a digital-to-analog converter (DAC). The DAC used has a current output. The 8-bit word applied to its input is converted into an analog current. This analog current is then rendered as a corresponding output voltage by the output operational amplifier. These output voltages are exactly as large as they were when sampled at the input of the input operational amplifier 100 clock periods earlier. The output samples are, however, delayed by the time T_t relative to the input samples, and this is precisely the dead time.
Dead time is directly dependent on the throughput speed of the digital pulses through the 100-bit shift register:
T_t = 100 · t_t (where t_t is the shift-register clock period)
At the output a staircase function is formed; each step corresponds to one input sample. (See Figure 2.)
The lower function in Figure 2 is an input function to the dead-time element; the upper function is the corresponding output staircase function. For a continuous periodic function, dead time manifests itself as a phase shift. The width of the individual steps is determined by the sampling frequency and directly by the clock frequency (Clock) of the shift register. It is therefore evident that the frequency of the input function must be smaller than the sampling frequency. The larger the ratio of input-function frequency to sampling frequency, the greater the number of steps of the staircase function per period.
Example:
- Input function: sinusoidal with a frequency of 1 Hz
- Sampling frequency: 50 kHz
-
With a sampling frequency (which is also the shift-register clock frequency) of 50 kHz, the dead time is: T_t = 100 · t_t = 100 / 50 kHz = 2 ms
-
The number of steps per output period is 50 kHz / 1 Hz = 50,000. At this high ratio the steps in the output function are barely visible on the oscilloscope.
3. Input Operational Amplifier
As already noted, the ADC can only convert voltages from 0 V to +10 V. The dead-time element is, however, to be able to process input voltages from –10 V to +10 V. To realize this requirement, the AD 503 operational amplifier is connected in the described manner.
The AD 503, connected as an inverting amplifier, compresses the range –10 V … +10 V to the range 0 V … +10 V (see Figure 3). The output voltage U_a of the AD 503 follows:
U_a = –(U_e · R4/R1 + U_ref · R4/R2)
Prescribed input resistors: R1 = 1 MΩ, R2 = 100 kΩ
Derived values: R3 = 1 MΩ, R4 = 500 kΩ, U_ref = –10 V
With the large input resistors R1 and R2, the goal is to keep the loading of the DO 80 computer by the dead-time element as small as possible. The resulting compression:
| Input U_e | Output U_a |
|---|---|
| +10 V | 0 V |
| 0 V | +5 V |
| –10 V | +10 V |
The voltages run in an inverted sense relative to each other; this is corrected by the output operational amplifier.
The 100 kΩ input is only usable when the input voltage is between +1 V and –1 V. The offset voltage of the AD 503 is compensated with a 10 kΩ pot, adjusted such that at 0 V input the AD 503 output is 5 V ±1 mV. The AD 503 supply voltages are ±15 V, decoupled with capacitors against ground.
A capacitor C1 (approximately 20 pF) can be connected in the feedback loop to prevent possible oscillation, but care must be taken not to make C1 too large, otherwise the frequency response of the AD 503 is degraded.
[Document includes the Analog Devices AD503J/K datasheet (English): high-performance FET-input op-amp, ±18 V supply, short-circuit protected, no external compensation required.]
4. Analog-to-Digital Converter
The output voltages of the input operational amplifier are converted into 8-bit words by the analog-to-digital converter (ADC 540-8). These 8 bits per word are output by the ADC in parallel. An 8-bit word corresponds to a binary number; with 8 bits one achieves a resolution of 1/2^8 = 1/256.
At +10 V at the ADC input, the converted 8-bit word is 11111111 (= 256). At 0 V the word is 00000000. For an ADC input voltage of +5 V, the converted 8-bit word follows: 5 V / 10 V × 256 = 128.
The most significant bit of an 8-bit word is called the Most Significant Bit (MSB); the least significant is the Least Significant Bit (LSB). The LSB corresponds to a voltage of 10 V / 256 ≈ 40 mV.
A conversion is initiated by an edge from the Strobe clock (generated by the VCO). The conversion time is 5 µs maximum. After this time the corresponding 8-bit word is available at the output and remains until the next Strobe pulse.
The ADC also outputs a Busy-Bit signal. The Busy-Bit is the same as the Strobe but is extended by the conversion time (~5 µs). With the falling edge of the Busy-Bit, conversion is complete. An important property: the converted 8-bit word is already available somewhat before the falling edge of the Busy-Bit — this is very convenient for the shift register.
The ADC output levels are TTL compatible:
- Logic “0” corresponds to 0 V to +0.8 V
- Logic “1” corresponds to +2.4 V to +5 V
The three supply voltages (+5 V, +15 V, –15 V) are decoupled individually with 1 nF capacitors.
[Document includes the Analog Devices/Hybrid Systems ADC 540-8 datasheet (English): 8-bit successive-approximation ADC, <5 µs conversion, 200 kHz sample rate, 0 to +10 V input range, 2” × 2” × 0.4” module.]
5. Shift Register
Shift registers in general consist of flip-flops connected in series so that the output of each flip-flop is connected to the input of the next. When information is applied to the input of this flip-flop chain, it is accepted by the first flip-flop at the next clock pulse. The subsequent clock pulse “shifts” the information to the second position of the register, while the first position accepts new information. After n clock pulses, an information item has been shifted by n positions in the shift register.
The complete shift register of the dead-time element is built with the integrated MOS device 2510k (Signetics). Four 2510k units are required, as each 2510k is a 2 × 100-bit static parallel shift register. 2 × 100 bits means the 2510k contains two shift registers of 100 positions each. To handle an 8-bit word one needs 8 shift registers, i.e., 4 × 2510k. The 2510k units are interconnected as shown in Figure 4.
So that an 8-bit word is accepted and then shifted, a clock pulse (Clock) is required. This Clock pulse is the inverted Busy-Bit from the ADC.
As mentioned, there must be synchronism between the ADC Strobe and the shift-register clock. The reason: the Clock for the shift register may arrive only when a fully converted 8-bit word is present at the ADC output.
The dead time depends solely on the shift register and the clock frequency:
Dead time = 100 × (1 / Clock frequency) = 100 × (1 / Strobe frequency)
The 2510k also has a “Recirculate” (circulating) facility. With Recirculate active: the input function is no longer sampled, while the contents of the shift register circulate cyclically and are continuously output to the digital-to-analog converter. The dead-time element can thus be used with the Recirculate function as a circulating memory that periodically reproduces any stored waveform.
To activate Recirculate, pin 10 of all four 2510k shift registers must be set to logic “0” (+0 V). Recirculate is deactivated by applying logic “1” (+5 V) to pins 10.
Supply voltages required by the 2510k: +5 V, 3 V, and –12 V. The 3 V and –12 V are derived from the –15 V supply via zener diodes.
6. Dead Time
The dead time is entirely dependent on the shift register and the clock frequency. Since Strobe, Busy-Bit, and Clock frequency are all equal:
Dead time = 100 / Clock frequency = 100 / Strobe frequency
7. Digital-to-Analog Converter
The DAC (DAC 371-8) converts the 8-bit words released by the shift register into an analog current. This conversion follows the scheme:
| 8-bit input word | Output current |
|---|---|
| 11111111 | ~2 mA |
| 10000000 | ~1 mA |
| 01000000 | — |
| 00000001 | — |
| 00000000 | 0 mA |
For the DAC output current: I_a ≈ (input binary value) × 2 mA / 256
The 2510k shift register has a “Three State” output that can float. Because it was not possible to establish from the DAC 371-8 datasheet whether input levels of –5 V could damage the DAC inputs, each DAC input is protected by a diode to ground. Resistors are inserted between the shift-register outputs and DAC inputs to limit the current the DAC must sink.
Maximum resistance value: R_max = 5 V / 6 mA ≈ 833 Ω → values selected from the datasheet
[Document includes the DAC 371-8 datasheet (English): 8-bit current-output DAC, <950 ns settling, single +15 V supply, 2 mA full-scale output, plug-in IC socket compatible, thin-film resistors.]
8. Output Operational Amplifier
The output current of the DAC is converted into a corresponding output voltage by the output operational amplifier. The relationship:
| DAC output current | Dead-time element output voltage |
|---|---|
| 0 mA | +10 V |
| 1 mA | 0 V |
| 2 mA | –10 V |
The output voltage is the same voltage that was sampled at the input of the dead-time element — delayed by the dead time.
The output operational amplifier used is also an AD 503, connected as shown in Figure 5.
Calculation of the feedback resistor: for I = 2 µA, U_a = –10 V must result: R = –U_a / I = +10 V / 1 mA = 10 kΩ
In the ideal case R = R_5 = 10 kΩ. To allow compensation of inaccuracies in the DAC and output amplifier, R_3 and R_4 are each replaced by a 9 kΩ resistor and a 2 kΩ potentiometer (Pot I and Pot II).
Calibration procedure:
- Pot I: set the dead-time element input to 0 V and adjust until the output is also 0 V.
- Pot II: set the input to +10 V and adjust until the output is also +10 V.
- R4 and R1 are 1% tolerance resistors with low temperature coefficient.
Summary of voltage transformations through the complete signal chain:
| Dead-time input | ADC input | Shift reg. / DAC input | DAC output | Dead-time output |
|---|---|---|---|---|
| +10 V | 0 V | 00000000 | 0 mA | +10 V |
| 0 V | +5 V | 10000000 | +1 mA | 0 V |
| –10 V | +10 V | 11111111 | +2 mA | –10 V |
9. Voltage-Controlled Oscillator (VCO)
The necessary Strobe clock for the ADC is generated by a Voltage-Controlled Oscillator (VCO). The VCO is connected as shown in Figure 6. The output clock frequency of the VCO is set by the voltage applied at socket 11. This voltage can be varied at the DO 80 computer via a ten-turn potentiometer between 0 V and –10 V. A voltage divider holds the voltage at pin 8 between 0 V and –4 V. At pins 4 and 5 a 1 kΩ resistor carries approximately 1 mA at full drive. The capacitor between pin 10 and ground determines the frequency range of the VCO.
For a frequency of 100 kHz (= 1 ms dead time): C = I / (f × V) = 1 mA / (10^5 × 10 V × 10^–5) = 1 nF
With the 1 nF capacitor, the theoretical frequency range is 100 kHz to 0 Hz. Practically the frequency can only be changed by a factor of 100:1, giving a usable range of 100 kHz to 1 kHz.
With a 10 nF capacitor: range 10 kHz to 100 Hz.
Relationship between control voltage, capacitor, and frequency:
| Voltage at socket 11 | Capacitor | Frequency |
|---|---|---|
| 10 V | 1 nF | 100 kHz |
| 1 V | 1 nF | 10 kHz |
| 0.1 V | 1 nF | 1 kHz |
| 10 V | 10 nF | 10 kHz |
| 1 V | 10 nF | 1 kHz |
| 0.1 V | 10 nF | 100 Hz |
| 4 V | 100 nF | 1 kHz |
| 4 V | 100 nF | 100 Hz |
| 4 V | 100 nF | 10 Hz |
The three capacitors (1 nF, 10 nF, 100 nF) can be selected via connections in the patch panel.
Calibration of the VCO potentiometer:
- Connect the 10 nF capacitor to pin 10; apply –0.5 V to socket 11.
- Adjust the 500 kΩ pot so that the frequency is 500 Hz.
- Then apply –5 V to socket 11 and adjust the voltage divider until the VCO covers the desired frequency range.
- With the 1 MΩ resistor at pin 4, the upper frequency limit is better defined.
[Document includes the Intersil 8038 Waveform Generator/VCO datasheet (English): precision sine, square, triangular, sawtooth, and pulse generator; 0.001 Hz to 1 MHz; FM and sweep capable; <1% THD; theory of operation with detailed circuit description.]
10. Control Logic (Steuerung)
The control logic has the following functions:
- Adapting the voltage levels of the DO 80 computer to those of the dead-time element.
- Protecting the various inputs and outputs.
- Adapting the dead-time element to the three operating modes of the DO 80: Initial Condition (IC/RS), Halt (HT), and Compute (DR).
In each operating mode of the DO 80, logic levels are applied to bus lines. The control logic connects to the DR and HT bus lines (Sammelschienen, SS). The levels on the bus lines for the three operating modes are:
| Mode | DR SS | HT SS |
|---|---|---|
| Compute | 0 | 1 |
| Halt | 0 | 0 |
| Initial Condition | 1 | 0 |
These levels are made TTL-compatible through a DO 80 standard interface circuit (see Figure 7). All digital inputs and outputs are short-circuit proof and reverse-voltage protected via the DO 80 interface circuit.
11. Operating Modes
The operating modes are explained with reference to the complete schematic on page 46.
Compute (Rechnen): DR SS = 0, HT SS = 1. These signals free the VCO, and its clock frequency is passed through a monoflop to the ADC Strobe. The monoflop (monostable, pins 4–12) ensures that the pulse width is always equal (1 µs) regardless of the VCO clock frequency. The inverted Busy-Bit is applied to the shift-register clock. In Compute mode the input function is delayed by the specified dead time.
Halt (Halt): DR SS = 0, HT SS = 0. Through an AND gate (pins 9–11) and an inverter (pins 8–9), the FET at pin 10 of the VCO is turned on. The conducting FET short-circuits the selected VCO capacitor. The VCO is stopped; its clock frequency is zero. Without a clock frequency the input function is no longer sampled, and the output holds the existing value.
Initial Condition (Anfangsbedingung): DR SS = 1, HT SS = 0. The input function is not sampled; the shift register contents are erased, and the output is brought to zero. This proceeds as follows:
- The VCO is again stopped via the FET.
- The Strobe is held high (logic “1”) through an AND gate (pins 1–4).
- While the Strobe is high, the ADC output adopts the 8-bit word 10000000.
- The word 10000000 at the shift-register input corresponds after 100 clock pulses to 0 V at the dead-time element output. All 100 positions of the shift register must therefore be loaded with 10000000.
- This process must be completed within 1 ms. The monoflop (pins 1–15) outputs a “1” signal for 1 ms at its Q output.
- The “1” signal from the monoflop starts an impulse generator built from a Schmitt trigger (pins 4 to 11). Its frequency is approximately 150 kHz. In 1 ms, more than 100 clock pulses are applied via a gate to the shift-register clock.
- With these clock pulses all positions of the shift register are set to 10000000 and the dead-time element output is 0 V.
Normal operation: In normal operation the 100 nF and 10 nF VCO capacitors are accessible in the patch panel. The DO 80 has an E key; pressing this key sends a pulse to the control logic. This pulse switches two latching relays so that the two accessible capacitors become 10 nF and 1 nF. The VCO frequency has thereby increased by a factor of 10.
Recirculate: The input function is no longer sampled; instead the shift-register contents circulate cyclically and are continuously output. While the dead-time element is in the Recirculate state, the Halt and Initial Condition modes behave the same — Initial Condition only halts the shift register without erasing its contents.
12. Patch Panel (Buchsenfeld)
- Sockets 1, 2, 3, and 4 are permanent connections (always active).
- Sockets 5 and 7 are the two inputs of the dead-time element. Socket 7 is the 1 MΩ input (full ±10 V range); socket 5 is the 100 kΩ input (usable only when the input voltage is between +1 V and –1 V).
- Socket 8 (and 3) is the output of the dead-time element.
- Recirculate mode is enabled by connecting socket 9 to ground (socket 10).
- Sockets 11, 18, 19 connect the HT bus line of the DO 80 to the control logic; connecting socket 17 to socket 20 connects the DR bus line to the control logic.
- Sockets 12, 14, and 16 select the VCO capacitor (1 nF, 10 nF, 100 nF).
- The dead-time element can also be driven by an external clock at socket 1.
- All connections in the patch panel are made with short-circuit plugs (Kurzschlussstecker).
13. Oscillograms
The oscillograms show the dead-time function: the upper trace is the input function to the dead-time element; the lower trace is the delayed output function.
14. Technical Data
| Parameter | Value |
|---|---|
| Input voltage range U_e | –10 V ≤ U_e ≤ +10 V |
| Output voltage range U_a | –10 V ≤ U_a ≤ +10 V |
| VCO control voltage range U_r | –10 V ≤ U_r ≤ –0.1 V |
| Total current consumption I_g | ~410 mA |
| Dead-time range T_t | 1 ms ≤ T_t ≤ 10 s |
| Operating modes | Halt, Initial Condition, Compute |
15–16. Complete Schematics
The document concludes with two full schematics:
- Overall view of the dead-time element (Gesamtbild des Totzeitglieds), page 55
- Complete control schematic (Gesamtschaltbild der Steuerung), page 55