English translation
Reference Sheets for the Analog Computer Laboratory
This document is an English translation of the German original “Hilfsblätter zum Praktikum Analogrechner,” produced at RWTH Aachen (Rheinisch-Westfälische Technische Hochschule Aachen) for the EAI Mini-AC analog computer laboratory course.
Table of Contents
| Section | Title | Page |
|---|---|---|
| 1 | Patchboard Layout (copy) | 3 |
| 2 | List of Components | 5 |
| 3 | Operating Modes, Central Control | 6 |
| 4 | Operating Principles of the Analog Element Types | 12 |
| 4.1 | The Potentiometers | 12 |
| 4.2 | The Integrators | 13 |
| 4.3 | The Summers | 16 |
| 4.4 | The Track-Store Units | 17 |
| 4.5 | The Multipliers | 19 |
| 4.6 | The Function Generators | 21 |
| 5 | Operating Principles of the Digital-Analog Element Types | 24 |
| 5.1 | The Comparators | 24 |
| 5.2 | The Switches | 25 |
| 6 | Operating Principles of the Digital Element Types | 26 |
| 6.1 | The Digital Control Section | 26 |
| 6.2 | Operating Modes of the Digital Control Section | 27 |
| 6.3 | The Frequency Divider (PULSES) | 27 |
| 6.4 | The Counter/Timer (CTR/TMR) | 28 |
| 6.5 | The Monostable Multivibrator (MONO) | 34 |
| 6.6 | The Gates | 36 |
| 6.7 | The Push-Button Flip-Flops (PBFF) | 38 |
| 6.8 | The J-K Flip-Flops (GPFF) | 38 |
1. Patchboard Layout (Copy)
Figure 1 shows the patchboard of the Mini-AC. The patchboard is divided into the following fields:
- Analog Field 1 (columns 11–16): Integrators/Summers, Track-Store units, Multipliers/Dividers, Function Generators (FG 26)
- Control Field (center): Central control switches, Selection, Display, Master Mode controls
- Analog Field 2 (columns 21–26): Summers, Multipliers/Dividers
- Analog Field 3 (columns 31–37): Summers, Multipliers/Dividers, VRO
- Logic Field: Gate controls, Flip-Flops (FF1–FF4), Counter/Timer, Monoflop, FF Enable, MONO
Figure 2 shows the field layout of the patchboard with detailed annotations of the individual regions: Analog Field 1, Analog Field 2, Control Field, Local Control, Master Mode, Logic Field, and Logic Gates.
Component symbols used in the patchboard diagram:
- I = Integrator
- S = Summer (Adder)
- T = Track-Store
- M = Multiplier/Divider
- FG = Function Generator
2. List of Components
The analog elements of the laboratory computer Mini-AC can each perform several functions. Switching between functions is accomplished via a switch on the respective plug card.
2.1 Analog Elements
The following analog elements are available:
- a) 6 Integrators/Summers
- b) 3 Summers/High-gain Amplifiers
- c) 3 Summers/Track-Store units
- d) 3 Multipliers/Dividers
- e) 2 variable Function Generators
- f) 18 Potentiometers
2.2 Digital-Analog Elements
The digital-analog elements include:
- a) 3 Comparators
- b) 3 Switches
2.3 Digital Elements
The digital elements include:
- a) 10 Gates
- b) 4 Flip-Flops
- c) 2 Push-Button Flip-Flops
- d) 1 Counter
- e) 1 Monoflop
- f) 3 Manual Switches
- g) 1 Frequency Divider
3. Operating Modes, Central Control
The analog control field contains the switches and a potentiometer for central control of the analog elements, as well as the three manual switches (MANual SWitch) and the power switch plus 2 rotary selector switches for output.
Six switches are available for selecting the operating mode: IC, HD, OP, PP, SP, SL.
3.1 SL (Slave)
The SL switch is used when coupling two computers. When pressed, the central control is taken over from the coupled computer (Master-Slave operation).
3.2 SP (Set Potentiometer)
The SP switch must be pressed to balance potentiometers used in a computing circuit.
The existing computing amplifiers are equipped with FET switches that react very sensitively to sudden application of an analog input quantity or to its removal.
Important: Set the computer to SP mode for all changes to the patched circuit and especially before and after switching off the power supply. In SP mode the FET switches are reset (gated) and protected.
3.3 IC (Initial Condition)
The IC switch sets all integrators and Track-Store units to initial conditions (Initial Condition).
3.4 OP (Operate)
The OP switch enables a one-time computation by removing the initial conditions of the integrators and connecting the summer summing points with the input resistors instead (OPerate).
3.5 HD (Hold)
The HD switch freezes computation values current at the switching instant by disconnecting the input resistors of the integrators (HolD).
3.6 PP (Patch Panel / Repetitive)
The PP switch is used for repetitive computation. In this operating mode, the IC and OP states alternate.
The length of the IC phase depends on the position of the FAST switch. If FAST is not pressed, the integrator feedback capacitors have value C = 1 µF and the IC phase lasts 0.7 s. If FAST is pressed, the capacitors have C = 2 nF (500 times faster computation) and the IC phase is 7 ms.
The length of the OP phase is adjustable in steps between 5 ms and 105 s using the TIMER potentiometer and the adjacent 4-position switch. The seconds decades 0.001, 0.01, 0.1, and 1 are selectable. The potentiometer sets a factor between 5 and 105, where the value shown in the dial window is multiplied by 10.
In PP mode the inputs and outputs of the TIMER control field and the Master Mode field are active (green = inputs, red = outputs).
Digital Inputs and Outputs of the TIMER and Master Mode Fields
Inputs:
3.61 RUN (TIMER) When RUN = 1, the timer is active. When RUN = 0, the sawtooth voltage resets to zero and remains there. When RUN = 1, repetitive operation begins with a normal IC phase.
3.62 H (TIMER) When H = 1, the sawtooth voltage remains at the value it reached at the switching instant (H: hold). When H = 0, the normal OP phase is ended.
3.63 H (MASTER MODE) When H = 1, the centrally controlled integrators go to the HOLD mode.
3.64 IC (MASTER MODE) When IC = 1, the centrally controlled integrators go to the IC mode.
Truth Table for Master Mode Control Inputs:
| IC input | H input | Resulting Operating Mode |
|---|---|---|
| 0 | 0 | OP |
| 0 | 1 | H |
| 1 | 0 | IC |
| 1 | 1 | H |
In the unconnected state the inputs IC = 1 and H = 0!
Important: Connecting the Master Mode control inputs IC and H is effective only in the PP (repetitive computing) mode.
Outputs:
3.65 PP, IC, OP (MASTER MODE) The PP, IC, and OP outputs each deliver a logic “1” signal when the central control is switched to the corresponding operating mode.
3.66 A, B, EB (TIMER) The signals A, B, and EB identify the OP phase (B = 1) and IC phase (A = 1) of repetitive operation; A = B̄. EB delivers a positive pulse of 1 µs duration at the end of the OP phase.
Figure 4 shows a timing diagram of the Timer and Master Mode signals during repetitive operation.
3.67 OL, ORH, OLS (MASTER MODE) The OL output delivers a logic “1” signal when a computing amplifier is overloaded (OverLoad). A brief override can be stored by connecting OLS with the OL signal (OverLoad Store). By connecting ORH with a logic “1”, a transition to the HOLD operating mode is forced (OverRide Hold). This connection has priority over all operating mode switches except SP.
3.8 Output
Using the rotary switches in the analog control field, the outputs of all amplifiers and the analog TIMER output can be switched to the corresponding jacks (SELECTOR 1 or SELECTOR 2) in the Readout field (Figure 2).
The jacks of the Display field are connected to the analog peripherals:
| Jack | Connection |
|---|---|
| 1 | Y1 (freely selectable peripherals, e.g. banana plug, oscilloscope) |
| 2 | Y2 |
| 3 | Y3 |
| 6 | X-deflection (hard-wired to x-y plotter) |
| 7 | Y-deflection |
At the START jack, the pen of the x-y plotter can be raised or lowered via a logic signal. With START = 1, the pen is lowered.
4. Operating Principles of the Analog Element Types
4.1 The Potentiometers
The potentiometers permit multiplication of a variable machine quantity by a constant factor less than one. All potentiometers are wired as shown in Figure 5.
Figure 5: Potentiometer wiring (IN → [potentiometer] → Output)
In SP operating mode, the potentiometers are balanced. For correct balancing, the potentiometers must be loaded with the load foreseen in the computing circuit; this means they can only be correctly balanced when the patch board is fully patched and the circuit is connected.
For balancing, the push-button next to the respective potentiometer is pressed. While the button is held, the setting of the desired value is read from the digital voltmeter.
During this process, in SP mode the input of the respective potentiometer is connected to 1ME and all amplifier input resistors at the summing input points are grounded.
4.2 The Integrators
The 6 available integrators each have 5 inputs and 3 outputs plus one input for setting the initial condition (Initial Condition). The input summing point is accessible for additional connections (Open Junction).
The feedback capacitance is C = 1 µF at normal computing speed and C = 2 nF when the FAST button is pressed.
The integrators can also be used as summers (switch on plug card). The feedback capacitance is then replaced by a resistor R_f = 1 MΩ. Two inputs labelled “10” have input resistances of 100 kΩ (“10” = factor 10); the three other inputs have 1 MΩ each (“1” = factor 1).
Figure 6: Internal wiring of an integrator (switch position: OP)
When the IC jack is connected to the initial condition (in IC mode), the output voltage u_A is:
u_IC = 0 for τ < 0 u_IC = U₀ for τ ≥ 0, R_IC = 10 kΩ
Figure 7: Applying initial conditions at the integrator
The transfer function is: {u_A} = -{i} · (1)/(sC + 1/R_IC) = -1/(1 + s·R_IC·C) · {u_IC} = -U₀/(s(1 + s·R_IC·C))
u_A = -U₀(1 - e^(-τ/T)), T = R_IC·C = {1 ms normal, 2 ms FAST}
Important: Each integrator has a local digital control field that can be connected to select an operating mode independently from the central control — local control has priority over the central control.
Switch positions for local integrator control:
| IC input | H input | Resulting Operating Mode |
|---|---|---|
| 0 | 0 | OP |
| 0 | 1 | H |
| 1 | 0 | IC |
| 1 | 1 | Centrally controlled |
Important: When using local control, both control inputs IC and H must always be connected. Note that in the unconnected state, the inputs IC and H have logic “1” level!
Figure 8: Truth table for local control of the integrators
4.3 The Summers
The 3 summers can be operated as open computing amplifiers (high-gain amplifiers) by switching on the plug card, in which case the feedback resistor of 100 kΩ is removed.
The input summing point is accessible for additional connections (Summing Junction). Each summer has 5 inputs, 3 of which have input resistance 100 kΩ (“1”) and 2 have 10 kΩ (“10”).
Figure 9: Internal wiring of a summer (switch position: OP, IC, H)
4.4 The Track-Store Units
The 3 Track-Store units are standard summers with additional properties: the output voltage can begin with a switched-up initial value (IC) and can be made equal either to the negative sum of the input voltages (Track) or to retain the value computed at the switching instant (Store), controlled by digital signals.
The control of the three operating modes IC, Track (T), and Store (S) is achieved via control inputs T and IC according to the following truth table:
Figure 11: Truth table for wiring the control inputs of a Track-Store unit
| IC | T | Resulting Mode |
|---|---|---|
| 1 | 0 | IC |
| 1 | 1 | IC |
| 0 | 1 | T (Track) |
| 0 | 0 | S (Store) |
Figure 12 shows a typical Track-Store operation with the timing of IC, T, S states, and the corresponding input and output voltages.
4.5 The Multipliers
The 3 multipliers each have 4 inputs and 2 outputs. They can also be used as dividers by switching on the plug card.
The core of this unit is a bipolar parabolic multiplier, which in turn consists of four summing circuits and two squaring diode function generators.
The internal wiring as multiplier and as divider is shown in Figures 13 and 14 respectively.
Figure 13: Internal structure of the multiplication circuit (switch position: OP, IC, H)
Z = -(N·D + A·B)
In Figure 13, N and D can be both positive and negative, but they must come from a low-impedance source (e.g. amplifier output; NOT from a potentiometer!).
Figure 14: Internal structure of the division circuit (switch position: OP, IC, H)
Z = (N·A·B)/D
For division, the denominator D must come from a low-impedance source just as in the multiplication circuit.
Important: For stable output Z, D > 0 must be satisfied. Additionally, to avoid overloading, |N| ≤ D must always hold!
4.6 The Function Generators
The two function generators can be operated either separately or coupled together.
In the first case, each of the function generators (FG) can approximate an arbitrary function from a maximum of 10 consecutive line segments; in the second case a function in the plane can be approximated by a maximum of 20 line segments. The choice of support points is free in the square x ∈ [-1ME, +1ME], y ∈ [-1ME, +1ME] provided that |dy/dx| ≤ 30.
Figure 15 shows the basic structure of a function generator.
The operating principle is briefly as follows: If the input quantity fed in via ‘IN’ is larger than X₀, diode D1 and Y₁ determine the current added at the summing point of the output amplifier to the current determined by Y₀, thereby setting the slope of the first line segment. An analogous process occurs when the input quantity becomes larger than X₁. Using the ‘GAIN’ switch, a fixed feedback resistor is switched into the output amplifier to set the maximum slope in the overall range.
Setting the MODE switch to ‘INV’ causes the output amplifiers of both function generators to act as pure inverters with the inputs labelled ‘I’.
Setting this switch to ‘20 PT’ (20 points), breakpoints 36 and 20 are settable at the function generator; element 37 then acts as a pure inverter with the input labelled ‘I’. The starting point of the generated function must be the leftmost point, and the function must not be multi-valued.
Setting breakpoints:
- Select IC mode.
- Turn the MODE switch to “11PT” (11 points) or “20PT” (20 points).
- Move the SET-OPER switch to “SET” (SET-OPERate).
- Set the GAIN switch to the desired maximum slope (1, 3, 10, or 30).
- Set the POINT switch to 0.
- Turn all X-potentiometers (X0–X10) fully clockwise.
- Using SELECTOR-1, select the function generator to be set (36 or 37).
- Set the start value for X (X0) according to the digital voltmeter display.
- Press the Y-SET key and, while pressing, set the desired Y start value according to the DVM display. Then release.
- Perform steps 8 and 9 for the other breakpoints similarly, setting POINT to the corresponding number before step 8.
- Correct the set function by repeating steps 8 through 10.
- After setting the last breakpoint, set POINT to OFF, SET-OPER to OPER, and check the set function with an oscilloscope.
Step 11 is necessary because the diodes used are not ideal elements and mutual influences occur when setting breakpoints. If the maximum slope turns out to be too small, a higher value must be selected and the process restarted from step 5.
Notes for 20-point function setting:
- a) X10 of FG36 is not used.
- b) X0, Y0, Y1 and GAIN of FG37 are not used. X1 of FG37 corresponds to X10 of FG36.
5. Operating Principles of the Digital-Analog Element Types
5.1 The Comparators
The comparators deliver complementary logic output signals as a function of the polarity of the sum of two analog inputs.
Figure 16: Circuit symbol of a comparator (two analog inputs → COMP → outputs C and C̄)
For a comparator as in Figure 16, the following truth table applies:
| Sum of Inputs | C | C̄ |
|---|---|---|
| positive | 1 | 0 |
| negative | 0 | 1 |
Figure 17: Truth table for wiring a comparator
If the logic latch input (L) is connected to logic “1”, the comparator is latched at the values present at the switching instant.
By pressing the button in the analog control field, a transition to the logically complementary state is forced.
The lamp in this button lights when C = 1.
5.2 The D/A Switches
A D/A switch switches an analog input on or off depending on a logic signal. With logic “1”, the analog input is passed through to the output.
Figure 18: Schematic diagram of a D/A switch (logic input + analog input → analog output via 10 kΩ)
The D/A switches can be connected to the input summing points of integrators and summers so as to switch additional analog quantities in and out (connection SJ–SJ or OJ–OJ).
Important: When the summing point of a summer or Track-Store unit is connected, the additional analog input has weight 10 (R = 100 kΩ); for an integrator however, the weight is 100 (R_input = 1 MΩ).
6. Operating Principles of the Digital Element Types
6.1 The Digital Control Section
Important: For digital signals (logic inputs and outputs), a logic “1” signal corresponds to a TTL voltage level of 5 V, and a logic “0” corresponds to 0 V. These levels are strictly to be distinguished from the analog levels +1ME (≈ +10 V) and 0 (≈ 0V).
Connecting digital inputs with analog quantities can lead to incorrect computation results!
Using the digital control section, it is possible to intervene directly in an ongoing computation, whether to control or stop it, or if necessary to take individual computing elements out of the loop. The digital control section consists of 10 AND-gates, 4 J-K Flip-Flops (GPFF), 2 Push-Button Flip-Flops (PBFF), 1 Counter (CTR/TMR), 1 monostable Multivibrator, 1 Frequency Divider, and a keyboard for selecting the logical operating modes.
For synchronization of all digital building blocks and for time-linking the digital elements with the analog elements, the Mini-AC uses a quartz-stabilized clock generator with a frequency of 1 MHz.
The keyboard of the digital control section and the lamp display for individual gates are located in the logic control field; the inputs and outputs are on the patchboard.
6.2 Operating Modes of the Digital Control Section
The three operating modes RUN, STOP/STEP, and CLEAR are selected with the corresponding buttons on the front panel.
6.2.1 RUN In RUN mode, the internal machine clock (1 MHz) is applied to all clock inputs of the logic elements. Synchronization with this clock equalizes the propagation delays of the individual digital elements. In RUN mode the RUN button is illuminated.
6.2.2 STOP/STEP (STP) By pressing STP in RUN mode, the machine clock is disconnected from the clock inputs (STOP). Each subsequent press of STP applies one clock pulse to the clock inputs (STEP). This allows manual clocking to carry out a test.
6.2.3 CLEAR (CLR) By pressing CLR, all flip-flops are reset and the CTR/TMR is set to zero. By pressing RUN or STP, operation switches to the corresponding mode.
6.3 The Frequency Divider (PULSES)
The frequency divider is an important part of the logical clock system, since it makes additional frequencies available to the program in addition to the machine clock: specifically 10², 10³, 10⁴, and 10⁵ Hz. The outputs of the divider, labeled PULSES, are on the patchboard. To the left of these is the C (Clear) input of the frequency divider. It operates when C is at logic “0”. When the RUN button is pressed, the FFs of the divider circuit are reset.
Output frequencies and periods:
| Output | Frequency | Period | Pulse duration |
|---|---|---|---|
| 10² | 100 Hz | 10 ms | 1 µs |
| 10³ | 1 kHz | 1 ms | 1 µs |
| 10⁴ | 10 kHz | 0.1 ms | 1 µs |
| 10⁵ | 100 kHz | 10 µs | 1 µs |
Figure 19: Frequency and period of the frequency divider outputs
6.4 The Counter/Timer (CTR/TMR)
Using the CTR/TMR keyboard in the logic control field, a number can be pre-selected and will be output by pressing a key on the CTR/TMR. The key for the selected number lights up and the lamp for the key whose corresponding FF is currently set burns. The current counter reading is the sum of the values of the illuminated keys.
As long as the CTR/TMR counts, there is a logic “1” at the counter output (TRUE) and correspondingly a logic “0” at the negated output (FALSE). Besides these two outputs, the counter has three inputs on the patchboard: CI (Carry In), S (Set), and C (Clear). The CI input receives the signal to be counted.
6.4.1 CTR/TMR as Counter
A logic “0” is applied to both inputs S and C (S = 0, C = 0). The signal to be counted is applied to the CI input (e.g., the zero crossings of a function, converted into a logic signal by a comparator). Provided that a brief pulse has been applied to input S, the counter counts as long as the count reaches the pre-selected number and then stops. Additionally, counting can be stopped when a logic “1” is applied to input C (S = 0, C = 1). This signal causes a reset of all flip-flops, reversing the outputs: TRUE → “0”, FALSE → “1”.
Figure 20: Pulse diagram of CTR/TMR as counter
Important: As input signals, the outputs of all logic building blocks as well as the outputs of the comparators can be used. Signal S can be of any length, but not shorter than 1 µs. Before the counting process begins, the counter must have been set up by pressing RUN; the internal clock must already be on.
6.4.2 CTR/TMR as Repetitive Counter
With a logic “1” at S and logic “0” at C (S = 1, C = 0), the counter counts the applied signal. When the counter reaches the pre-selected number n, the counter output transitions: FALSE → log. “1”, TRUE → log. “0”. (The state TRUE = log. “0” lasts only one clock pulse, 1 µs.)
With the trailing edge of the next machine clock, the flip-flops of the binary counter are reset and the new counting process starts. With the same trailing edge, the counter output switches back to the old state: FALSE → log. “0”, TRUE → log. “1”.
If S and C are connected simultaneously, a brief pulse at C causes the counting to stop immediately. The same occurs when the CLEAR key is pressed.
Simultaneously applying a permanent logic “1” at both S and C (S = 1, C = 1) creates an undefined state.
Figure 21: Pulse diagram of CTR/TMR as repetitive counter (n = 2 selected)
6.4.3 CTR/TMR as ONE-SHOT
Some problems require an input or control signal of a defined duration. These can be generated with the CTR/TMR. If one of the four frequencies of the frequency divider is applied to input CI and a counting quantity n is pre-selected (brief pulse on Set input S), the counter increases the count (brief pulse on set input S) and pre-selects a number n of pulses to count. The CTR/TMR can stop a computation at a certain point in time, or let it repeat at certain intervals. It can also send brief signals to steer or monitor a running program.
For example, if a signal of duration 1 s is needed, apply the 10² Hz clock to CI. Counting 100 pulses and noting that the period of the applied pulses is T = 1/100 = 0.01 s, the counter output TRUE = 1 for 100 × 0.01 s = 1 s.
ONE-SHOT duration table:
| CI frequency | n | ONE-SHOT Duration |
|---|---|---|
| 10² (T = 0.01 s) | 100 | 1 s |
| 10 | 0.1 s | |
| 10³ (T = 1 ms) | 100 | 0.1 s |
| 10 | 10 ms | |
| 10⁴ (T = 100 µs) | 100 | 10 ms |
| 10 | 1 ms | |
| 10⁵ (T = 10 µs) | 100 | 1 ms |
| 10 | 0.1 ms |
Figure 22: Relationship between applied pulses and output signal duration
Truth Table of CTR/TMR (Figure 24):
| S | C | Counter Operation |
|---|---|---|
| 0 | 0 | Counter remains reset |
| 1 | 0 | Counter set, operates repetitively. If n is only a brief, one-time pulse at S, counter counts to the pre-selected number and stops. |
| 0 | 1 | Counter stops if it was previously active; otherwise counter remains reset. |
| 1 | 1 | Undefined state |
It is assumed in Figure 24 that a counting pulse is continuously applied to CI.
6.5 The Monostable Multivibrator (MONO)
With the monoflop, an output pulse of a defined duration can be generated when the input is activated by a trailing edge. The time shown in Figure 25, after which the monoflop resets, can be varied by the external potentiometer (25 kΩ) and also by externally connected capacitors, thereby altering the pulse width of the output signal. The time is determined by:
t_OUT = ln 2 · R · C ≈ 0.7 · R · C
Figure 25: Monostable multivibrator (Texas Instruments SN 74121 N) with variable output pulse width. Capacitor values: 0.01 µF, 0.1 µF, 1 µF, 10 µF, 100 µF, 1000 µF.
The selection of capacitors and the setting of the potentiometer are made externally by means of a continuous potentiometer and a stepped rotary switch in the logic control field. Input and output are on the patchboard.
6.6 The Gates
6.6.1 Structure and Function of AND Gates
The logic control section of the analog computer has 10 AND-gates. Their inputs and outputs are also on the patchboard. Six of these gates have 2 inputs and the remaining gates have 4 inputs.
Figure 26: Structure of Gates 1 to 6 (A·B → output X = A·B and X̄ = Ā·B̄)
Figure 27: Structure of Gates 7 to 10 (A·B·C·D → output X = A·B·C·D and X̄ = Ā·B̄·C̄·D̄)
If the AND-gate output has a logic “0” signal, the corresponding lamp in the logic control field lights up. The gate inputs are designed so that with no connection (unconnected), a logic “1” is present at the input.
6.6.2 Applications of AND Gates
In addition to their use as AND or NAND gates as explained in Figures 26 and 27, the gate output levels can also be used as logic signals for control inputs. Further wiring possibilities:
Figure 28: Logical Inverter (single gate with input A → output Ā)
Figure 29: OR circuit: (A·B·Ā·B̄) → outputs X̄ = Ā·B̄·Ā·B̄ and X = A·B
Figure 30: Cascade circuit: 8-input AND gate (A through H → X = A·B·C·D·E·F·G·H)
6.7 Push-Button Flip-Flops (PBFF → Push-Button-Flip-Flop)
Two groups of buttons are in the logic control field, labeled PB1 and PB2. They serve to control the two available Push-Button Flip-Flops (PBFF). After pressing key S, the PBFF is set with the trailing edge of the next machine clock, and the key illumination lights. A press of key C resets the PBFF, and the illumination of key S goes out. The PBFF outputs are on the patchboard. If one of the PBFFs is set, its TRUE output is logic “1”.
General reset of both PBFFs occurs by pressing the CLR key.
6.8 J-K Flip-Flops (GPFF → General-Purpose-Flip-Flop)
The digital control section of the Mini-AC has four GPFFs. Their control keys, labeled FF1, FF2, FF3, and FF4, are in the logic control field; their inputs and outputs are on the patchboard. The GPFFs can be operated manually via the control keys: pressing key S sets the corresponding GPFF; pressing key C resets it; pressing CLR resets all generally.
Via the patchboard, each FF is additionally controllable externally. Each FF has three inputs: S (Set), C (Clear), and EBL (FF Enable). With the trailing edge of EBL, the FF is clocked. At the inputs, logic “1” level is present in the unconnected state.
The static signals from the keys act as set and reset inputs of the J-K Flip-Flop and have priority over the dynamic input signals.
Figure 31: Circuit symbol (DIN 40700), state table, and characteristic equation of the GPFF J-K Flip-Flop
Q^(n+1) = J^n · Q̄^n + K̄^n · Q^n
Applications of GPFFs:
Figure 32: Delaying signal X by one pulse width of the clock signal EBL
Figure 33: “Differentiation” circuit (two gates + GPFF)
Figure 34: Wiring the GPFFs as a shift register
If the information X to be shifted is manually set in FF1 (pressing key S), and the outputs of FF4 are connected to the inputs of FF1, a closed shift register is realized.
End of translation. This document covers 40 pages of German-language laboratory reference material for the EAI Mini-AC hybrid analog computer, produced by RWTH Aachen for student practical laboratory use.