Analogrechner Dornier 80 Bedienungs-Handbuch

Complete English translation of the original German-language document (96 pages).

[page 1: cover page — DORNIER SYSTEM. Document number 289/2-23. Lending stamp: Lehrstuhl und Laboratorium für Steuerungs- und Regelungstechnik, Technische Universität München, Arcisstraße 21, 8000 München 2. “Ausleihdauer 1 Woche” (Loan period 1 week). ANALOG COMPUTER — DORNIER 80 — Operating Manual. Dornier System GmbH, 7990 Friedrichshafen, Postfach 645. Telephone: 07545 – 81, Telex: 01 – 34258. January 1976.]

1. Introduction

The present operating manual for the analog computer DORNIER 80 is intended to serve two principal purposes:

For those operating the DO 80 for the first time, it provides the guidance necessary for operating and programming the machine.
For those already experienced, it is intended to serve as a reference work for special circuits.

This manual presupposes a basic knowledge of analog computing, so that explanations of the theory of programming or of analog computation are not provided. For this purpose, reference is made to the Dornier publication “Introduction to Analog Computing.”

2. Layout of the Computer

Figure 2.1: Front view of the DORNIER 80

Figure 2.1 shows a front view of the DORNIER 80. On the right-hand side, the operating and display panel is visible. On the left-hand half are the four potentiometer plug-in slots and below these the 16 plug-in slots for the computing elements. Each of the 16 slots can accept a plug-in computing element, with all 16 slots being interconnected by parallel wiring (Figure 2.2).

[page 4: figure only]

Figure 2.2: Parallel wiring of the individual plug-in slots

This results in a very large number of possible component combinations.

The individual operating and display elements are described in Chapter 3.

3. Description of the DO 80 Unit

Figure 3.1 shows a front view and Figure 3.2 a rear view of the computer. The individual operating and display elements have the following meanings and functions:

Trimming potentiometer for +10 V reference voltage.
Trimming potentiometer for −1 V reference voltage. The trimming of the reference voltage is carried out in accordance with the technical documentation.
Display field for the output of the comparators, maximum four. The lamp is lit when the sum of the input voltages at the comparator is negative.
Overrange display field. For each of the 16 plug-in slots there is a lamp in this field. The lamp lights up when the output voltage of the computing element in that slot exceeds a value of approximately ±10.8 V. In addition, it provides an indication for each integrator: at the integrator plug-in slot, it also signals a positive or negative reference voltage, e.g. by a patch through a resistor (e.g. ±9.95 V).
Analog voltmeter for displaying the operating voltages and measuring analog quantities, with three switchable ranges. The voltmeter includes an input transistor amplifier. The voltmeter is tested in the BT unit.
Switch for automatic HALT on overrange. If switch SUT is in the upper position, it simultaneously actuates the overrange display of the computer and places the computer in the BT unit. This is tested in the BT 27 unit.
Input jacks for the voltmeter preamplifier. Figure 3.3 shows the voltmeter connections.

[page 6: figure — schematic representation of the voltmeter arrangement]

Figure 3.3: Schematic representation of the voltmeter arrangement

The lower (yellow) bus is normally switched out by Switch 8, so that it also has a high-impedance input free of the preamplifier. In position DIFF (= differential), Switch 8 connects the second input to the voltmeter so that the voltmeter displays the sum of the two input voltages.

Two-position selector switch for the voltmeter. With this switch the following can be measured:

Switch position	Measurement range	Purpose
+5 V	±15 V	Control of the internal supply voltages
−15 V	±15 V
+15 V	±15 V
+Ref.	±15 V
−Ref.	±15 V
±1	±15 V	Measurement at the jacks of the upper (yellow) bus 7
Abl.	±15 V
Diff.	±150 mV	Measurement of the sum of the voltages at both buses 7

Zero adjuster with display lamp.
Single-turn potentiometer for compute time. The product of the potentiometer 10 setting and the switch 11 setting gives the compute time in the OPERATE mode and the RR (Repetitive Run) integrating time. The computer is in the RESET (“Initial Condition”) state for the time t_p.
Selector switch for coarse setting of the compute time. Using this switch and Potentiometer 10, the compute time can be varied in the following ranges:

Switch 11 position	t_p	Compute time t_B
0.1 sec	0.1 sec	0.1 bis 1.1 sec
1 sec	0.1 sec	1 bis 11 sec
10 sec	1 sec	10 bis 110 sec

The compute and reset times are reduced to one-tenth of the above values by Switch T/10 (21).

Setting potentiometer for reset time. The 11 input potentiometers in the limit value hold, which would be connected to the analog potentiometers as memories, are a continuously adjustable reset time. This is achieved by Potentiometer 12.
REMOTE (external) switch. This switch makes the DORNIER 80 operable as a slave machine (Master-Slave operation). The timing generator of the slave machine is then disabled, and instead the common REMOTE signals of the master machine — which is able to trigger up to 15 units simultaneously — are made available.
REMOTE indicator lamp. When a slave machine is connected to the DORNIER 80, the lamp lights up.
AB key. Pressing this key brings the computer into its OPERATE mode (AB = Arbeitsbetrieb). Pressing AB and simultaneously pressing Switch 11 produces a momentary integrating operation corresponding to the set value. The computer subsequently returns to the RESET state and delivers −10 V continuously at the output.

In the BT unit:
- SW 8: transistor locked (de-energized)
- SW T: transistor conducting (energized)
HT key. Pressing this key puts the computer into the “HALT (Hold)” mode. Pressing HT at the end of the compute time holds the computer at the last value reached. The computing elements remain at their momentary output values.

In the BT unit:
- SW 8: transistor locked (de-energized)
- SW T: transistor conducting (energized)
DR key. Pressing this key activates the REPETITIVE RUN mode and thus starts repetitive operation. The timing alternates between the set compute time and the set reset time. The operating mode alternates between the compute and reset states.

The BT unit provides the following indication:
- SW 8: transistor locked (de-energized)
- SW T: transistor conducting (energized)
In the REPETITIVE RUN mode, the output voltage varies from −10 V to +10 V over the compute time and then returns in an external feedback ramp. This makes an analog representation of the computation available.
Taste 1×-Betrieb (1× key). Pressing this key brings the computer into the single-run mode. After pressing it — as well as following any subsequent AB actuation — the computer executes exactly one compute cycle in accordance with Switch 11 and then halts. The Halt transistors DR (17) monitor this process:

In the BT unit:
- SW 8: transistor locked (de-energized)
- SW T: transistor conducting (energized)
RR key. Pressing this key puts the computer into the “REPETITIVE RUN (Registered Run)” mode and thus starts periodic operation. The timing generator then operates repetitively and the repetitive integrators are incorporated. The compute and reset times are set by Potentiometer 10 and Coarse Switch 11 and the corresponding integrators are set from there accordingly. In the DR mode, the output voltage ramps from −10 V to +10 V and in the RESET mode, the external Betriebsrücklaufspannung (return-run voltage) ramp is available. An external decrement from register control may also be available.
mHT (momentary HALT) key. After pressing the mHT key, the computer assumes the HALT state and thus freezes the computation result. After re-releasing the key, the computer resumes from the halted position.

In the BT unit after pressing mHT and after pressing HT HALT:
- SW 8: transistor locked (de-energized)
- SW T: transistor conducting (energized)
After pressing mHT and after pressing HALT, the computer goes into the HALT state and at the same time the output of the computer halts to keep the lamp on.
T/10 key. Pressing this key reduces the compute and reset times of the computer to one-tenth of the set values.

At RR “HALT” and at “ALT HALT”, the timer control also stops the BT unit. The individual transistors switch simultaneously with the set value and deliver −10 V in the RESET state following this. The computer then returns to +10 V. By rapid actuation of the mHT key, it is possible to continue the computation for a defined limited interval.

On the rear of the computer the following jacks are located:
Patch field.

[page 13: figure — patch field diagram of the front programming area]

Legend:

PT, DR: These jacks are identical to the correspondingly labelled jacks on the front programming field.
RTF, DR1: RTF and DR1 are the control signals of the timing generator. They are identical in their operating modes to OPERATE and REPETITIVE RUN. In the OPERATE mode, at the correspondingly set value, they provide a relay-free signal for external devices (e.g. as pushbutton contact in X–Y control).
TAB, TOT, TDR: These single inputs connect the respective keys AB, HT, DR in parallel. Through the connection of these jacks, it is possible to trigger the corresponding operating modes from external devices. Thus a simple frequency measurement of the computer is possible.
RAMPE: At this jack, the timing generator provides an analog output signal of the timing generator.

[page 14: figure — timing diagram showing the RAMPE output voltage waveforms for the operating modes AB, DR, HT, DR]

Timing diagram

External connections A, B, C, D: At the jacks, these are the pot fields A, B, C, D with T₁, T₂ associated connections respectively.
Ground jacks: Three ground jacks and two chassis jacks.

Synchronization connector from/to further DORNIER computers. [page 15: figure — synchronization connector pinout diagram]

The computer provides synchronization signals for parallel operation with further DORNIER machines. These signals cover the operating modes OPERATE and REPETITIVE RUN as well as the overrange display. The signals are TTL-compatible in positive logic. The coupling of the computer with up to 4 machines is accomplished by simple connection of Jack 24.
External connections at the jack on the front programming field. Instruments (e.g. recorder, oscilloscope) can be connected via these jacks. The connection of the output is made through an external register. Via this jack, it is possible to take the parallel output of a second computer and couple it with the patch field of the second computer.

[page 16: figure — rear panel connector diagram showing sockets A, B, C, D with T1, T2 pins, ground symbol (⊥)]

Mains fuse.
Mains plug.
Test jacks for the internal supply voltages.

4. Operating Mode Control and Timing Generator

4.1 General

Figure 4.1 shows the keys for controlling the operating modes.

Figure 4.1: Control keys for operating modes

Key 15	Key 16	Key 17
AB	HT	DR

Key 18	Key 19	Key 20	Key 21
1×	RR	mHT	T/10

The significance of Keys 15 to 21 has already been described briefly in Chapter 3 under those item numbers. Here the interaction of the timing generator with the operating modes 15 to 21 is explained in detail once more.

4.2 Operating Modes AB, HT, and DR

When none of the pre-selection keys 18 to 21 has been pressed, the timing generator delivers a ramp voltage at the jacks designated RAMPE on the rear of the computer, in accordance with Figure 4.2.

[page 18: figure — timing diagram showing the RAMPE output voltage waveform]

Figure 4.2: Output voltage of the timing generator

The times t_R and t_P are set at Potentiometer 10 and Switch 11 or at Potentiometer 12 respectively.

These times are reduced to one-tenth of the set values by Key 21 (T/10).

4.3 1x Compute (1x Rechnen)

When the 1x key is pressed (illuminated), pressing the DR key initiates a single compute pass as shown in Fig. 4.3.

Fig. 4.3: Timer output voltage during 1x Compute

The figure shows the timer output voltage rising linearly from -10 V to +10 V during the compute time t_R (DR mode), then dropping sharply back and holding through the hold/display time t_p (AB mode), after which the machine returns to AB mode. The operating mode sequence is: AB → DR → AB.

After the compute time has elapsed, the computer returns automatically to operating mode AB. The T/10 key reduces the times t_R and t_p to one-tenth of the set values.

4.4 1x Compute “With Halt” (1x Rechnen “mit Halt”)

When keys 18 (1x) and 20 (mHT) are pressed, the timer delivers the output voltage shown in Fig. 4.3. After the compute time t_p has elapsed, the computer switches to operating mode HT rather than AB.

A renewed start is possible by pressing the DR key, but without first pressing the AB key.

4.5 RR (Repetitive Compute / Repetierend Rechnen)

When key 19 (RR) is pressed, each press of the DR key initiates a repetitive compute sequence as shown in Fig. 4.4.

After the compute time has elapsed (t_p), the computer returns automatically to AB mode, and then immediately begins a new repetitive compute pass (Repetierdurchgang).

The T/10 key reduces the times t_R and t_p to one-tenth of the set values.

Note: This applies as well when 1x Compute and RR are not pressed.

Fig. 4.4: Timer output voltage during RR (Repetitive Compute)

The figure shows repeated triangular waveforms cycling through AB → DR → AB → DR … each cycle consisting of a linear ramp up during DR, followed by a brief AB phase, with the cycle triggered by pressing the DR key.

4.6 Repetitive Compute “With Halt” (Repetierend Rechnen “mit Halt”)

When keys 19 (RR) and 20 (mHT) are pressed, and the DR key is subsequently pressed, the sequence proceeds as shown in Fig. 4.5.

Note 4) This is the same behavior as when started from a prior run or from a special initial condition. The ramp can be reset from +10 V by switching back to AB; this allows restarting the repetitive compute pass from the initial state of the 1st pass.

[page 22: figure only — Fig. 4.5]

Fig. 4.5: Timer output voltage during Repetitive Compute with Halt (RR, mHT)

After the set compute time t_R has elapsed, operating mode HT is engaged and the ramp remains at +10 V.

The ramp shows the same progression in operating mode DR mHT (i.e., without RR). In this case the mHT supplement serves the following primary purpose: when recording a result on an XY-recorder, in modes RR mHT or DR mHT the recorder arm moves to the end position —

[page 23: continues previous paragraph]

— does not move over the recording, so that the result can be observed at the XY-recorder without manipulation. In 1x Compute, this can also be achieved by mHT.

4.7 Segment-by-Segment Compute with Defined Times (Abschnittsweises Rechnen mit definierten Zeiten)

If a computation is to be interrupted in segments, the following procedure is used:

In HT mode: During the compute time t_R the computation runs; it is then switched to HT (hold). The computer is ready for the 1st pass. The IC output represents the initial state of the 1st pass (kein Eingriff = no intervention in the interrupted process). The IC output is the initial state of the 1st pass (Repetierdurchgang).
Press DR key: The 2nd pass is started and t_p is measured again.

Note: If the process was started from an initial condition or after pressing the AB key, the ramp can be reset from +10 V back to -10 V by switching to AB, allowing the repetitive compute pass to begin again from the initial state.

5. Summator Module (Summierer-Einschub)

5.1 Patch Panel Connections (Steckfeldanschlüsse)

Fig. 5.1: Patch panel connections of a summator module

Each summator module contains only two tiers (Einschübe) of hardware depth 3. The wiring diagram is shown in Fig. 5.2. Each summator module has one input and two feedback paths as well as one output; these are accessible at the patch panel. (See Fig. 5.1.)

The upper summator has four inputs and one output. It can be configured as either a single-input or dual-input summator as well as with an output amplifier. (See Fig. 5.1.)

The lower summator is an open-collector type with four inputs, two feedback inputs and two reference inputs. This is the standard point for coefficient settings.

Note: A non-feedback (non-returning) connection can lead to triggering of the overload indicator.

[page 25: figure only]

Fig. 5.2: Circuit of the upper summator

Fig. 5.3: Circuit of the middle summator

Fig. 5.4: Circuit of the lower summator

The three figures show block-level schematic diagrams of the upper, middle, and lower summators respectively. Each consists of configurable input resistors (labeled 1, 10) feeding an inverting operational amplifier, with output connections (SP = Summierpunkt = summing point) indicated at the patch panel.

5.2 Programming (Programmierung)

The operating principle and programming of the summators is explained by means of the following examples.

Symbol	Wiring (Beschaltung)	Operation
x1, x2 → Y1 (upper summ.)	x1 via input weight 1; x2 via input weight 1	Y1 = -(x1 + x2)
x3, x4 → Y2 (middle summ.)	x3 via weight 1; x4 via weight 10	Y2 = -(x3 + 10·x4)
x5, x6 → Y3 (lower summ.)	x5 via weight 1 (SP); x6 via weight 10	Y3 = -(x5 + 10·x6)

Fig. 5.3 (page 27): Additional programming examples

Symbol	Wiring	Operation
x1 → Y1 (upper summ.)	x1 via weight 1, one output tied back via weight 1	Y1 = -x1/2
x2, x3 → Y2 (middle summ.)	x2 and x3 via weight 10; output at SP	Y2 = -5·(x2 + x3)
x4, x5, x6 → Y3 (lower summ.)	x4 via weight 1; x5 via weight 1; x6 via weight 10	Y3 = -(0.1·x4 + x5 + 0.1·x6)

Fig. 5.4 (page 28): Programming with potentiometer feedback

This shows configurations using potentiometers P1 and P2 for coefficient scaling:

Upper summator with P1 in feedback (position alpha_1): Y2 = -x_e · 1/(1 + alpha_1)
Lower summator with P2 feedback (position alpha_2): X5 = -(x3 + 10·x4) / alpha_2

6. Integrator Module (Integrierer-Einschub)

6.1 Patch Panel Connections (Steckfeldanschlüsse)

Fig. 6.1: Patch panel connections of an integrator module

Each integrator can also be used as a summator (see section 6.2). Additionally, each integrator can be individually controlled in its operating modes and time constants (see section 4.2). The individual controllability of each integrator for operating modes and time constants (Initial Condition/Hold/Compute) is described in section 6.2.

The wiring of a single integrator and the more detailed description of the individual patch panel connections is shown in Fig. 6.2.

Note: A non-feedback (non-returning) connection can lead to triggering of the overload indicator for summators/integrators.

[page 30: figure only]

Fig. 6.2: Circuit of an integrator (shown in Hold/IC position)

The figure shows the full schematic of one integrator block. The patch panel connections include multiple weighted inputs (via resistors labeled with gain values), a feedback capacitor network, control bus lines (HT and DR buses labeled at the top), and the output labeled Y/IC. The integrator is shown in the IC (initial condition) hold state, with the IC input connected through the hold switch network.

Buses B and S carry the operating mode control supply. These buses lie (Fig. 6.1) directly beside the outputs of the operating-mode control buttons HT and DR.

6.2 Operation as Integrator (Betrieb als Integrierer)

To operate the unit as an integrator, the module must be wired as shown in Fig. 6.3.

For this, one integration amplifier and one summing amplifier (see also section 6.2) are provided, along with a feedback connection of the output back to the summing amplifier (IC feedback connection, Fig. 6.1). The der Ist-Ausgangswert (actual output value) is connected back via the IC bus.

Each integrator is to be provided with its individual DC control for operating modes and time constant, but must be connected with buses HT and DR for collective (bus) control, using switches B and S, according to the following truth table:

[page 32: table and circuit diagram]

Operating mode control table:

Commanded mode	Bus HT	Bus DR
AB	Relay-connected	open
DR	open	Relay-connected
HT	Relay-connected	Relay-connected

The designation “Relay-connected” (Relaiserde) and “open” (offen) is to be understood as follows: the buses represent an “open-collector output” per Fig. 6.4. “Relay-connected” means a conducting output transistor; “open” is produced by a blocked (non-conducting) output transistor.

Fig. 6.4: Supply of the buses (Versorgung der Sammelschienen)

The figure shows the open-collector driver circuit for the DR bus: a transistor with its collector connected to the bus line and emitter to relay ground (Relaiserde), driven by the DR signal. A relay coil connected to +12 V is energized when the transistor conducts.

6.3 Time Constant Change (Zeitkonstanten-Änderung)

For each integrator, a selection among three different time constants is available (see also Fig. 6.2):

Via shorting plug (Kurzschlussstecker) on the programming panel, individually selectable per integrator.
Via the T/10 key, globally for all integrators.

The following truth table gives the applicable time constant for each case:

Connection between patch pins (X…)	T/10 key	Feedback factor	Time constant (Std. = 1 Sec)
X : 1	not pressed	1	1 Sec
X : 10	not pressed	0.1	1 Sec
X : 1	pressed	0.1	0.1 Sec
X : 10	pressed	0.01	0.01 Sec

6.4 Operation as Complementary Integrator (Betrieb als komplementärer Integrierer)

An integrator wired per Fig. 6.1 operates as a complementary integrator. The only difference from the standard wiring (Fig. 6.1) lies in the horizontal arrangement of the two shorting plugs on the programming panel. As the following table shows, this makes the operation of the complementary integrator the inverse of a normal integrator:

Fig. 6.5: Wiring for operation as complementary integrator

The figure shows the plug arrangement difference between normal and complementary integrator wiring in the patch panel.

Commanded computer mode	Normal integrator mode	Complementary integrator mode
AB	AB	DR
DR	DR	AB
HT	HT	HT

6.5 Operation as Summator (Betrieb als Summierer)

An amplifier wired per Fig. 6.6 operates as a summator (inverting summer). Its wiring is similar to the integrator-summator connections described in section 6.2. Fig. 6.6 shows that for the input S (signal input) the output of the amplifier is taken directly via the IC output; such signals can be tapped from the amplifier. These are described in section 6.6.

Fig. 6.6: Wiring for operation as summator

6.6 Special Circuits (Spezielle Schaltungen)

The following presents a selection of special circuits and operating forms of the summator/integrator module. This selection is certainly not exhaustive of all possibilities. Its purpose is to illustrate an array of options, and in particular to point out some unusual circuits that diverge from standard practice, as well as what these departures can lead to in terms of computing element behavior.

[page 36: figure only]

Fig. 6.8: Special circuit examples (three panel configurations)

Three side-by-side diagrams of the integrator/summator patch panel are shown, each with different wiring configurations:

Left panel:

Y2 = -(x1 + 10·x2)
and Y1 = x2

The wiring shows x1 and x2 inputs to the upper section; x2 feeds through to Y1 directly (unity gain path), while x1 and x2 weighted combine at the lower amplifier to produce Y2.

Middle panel:

y = -(y1 + 10·x2)
(legend: R = Relaiserde/relay-ground; o = offen/open; S = offen/open)

The center panel shows a configuration with:

AB: offen, Relaiserde
(operating mode connections shown)

Right panel:

Y = -(0.2·x1 + x2 + x3)
(partial text: “kurz geschlossen” = short-circuited)

The right panel wiring shows three inputs x1, x2, x3 with different weighting through the resistor network to produce the scaled summation output Y.

Page 37 — Figure only (schematic diagrams with annotations)

[page 37: figure only — three panel diagrams showing circuit configurations for an integrator or multiplier module. Left panel legends: H = open, Y = rückwärts (reverse), V = 0. Center panel formula and notes: Y = -y_0 + (1/2) ∫ (1 + 0·y_1) dt; notes on Betrieb (operation) with positive/negative Vorverstärker (pre-amplifier), normalized variable, and with Anfangsbedingung (initial condition) with various Betriebszustände (operating states). Right panel legends: Prüf- & Steuer-Bereich: S = offen (open), S = Rücksetz-Phase (reset phase), Betriebszeit: Klaus (see text section 7(3)).]

7. Multiplier Plug-In Unit

7.1 Plug-In Connectors

Figure 7.1 shows the plug-in connectors of a multiplier plug-in unit.

The upper and lower slot each accommodates a single multiplier. Three potentiometers are available per plug-in unit, while the fourth has a zero-point adjustment. These potentiometers are freely accessible before the operational amplifiers are installed, so they can already be set with all trimmer potentiometers populated.

Figure 7.2 shows the schematic circuit of the computing element of a multiplier plug-in unit.

Note: A thin-film multiplier can, under certain circumstances, lead to an overrange response.

[page 38: figure — plug-in connector diagram for a multiplier plug-in unit, with three panel rows showing individual connector positions. Caption: “Fig. 7.1: Plug-in connectors of a multiplier plug-in unit.”]

Page 39 — Figure only

[page 39: figure only — four schematic circuit diagrams showing different computing-element configurations of a multiplier plug-in unit. Top diagram shows the basic network/amplifier arrangement; subsequent diagrams show configurations with labeled resistors (R100Ω, R20Ω). Bottom diagram again shows the full arrangement with a network block. Caption: “Fig. 7.2: Schematic circuit of the computing element of a multiplier plug-in unit.”]

7.2 Operation as Multiplier

The circuit shown in Figure 7.3 causes the multiplier to form the product of its two input variables x₁ and x₂:

y = x₁ · x₂

Here x₁ and x₂ are normalized variables that move freely between 0 and 1.

Fig. 7.3: Circuit as multiplier

In terms of voltages, the following relationship holds:

U_y / 10 V = (U_x₁ / 10 V) · (U_x₂ / 10 V)

where U_x₁ and U_x₂ are the input voltages and U_y is the output voltage.

Note: The source resistances remain essentially constant; for x, 10 mΩ and for y, 12.5 kΩ; for z, 34 kΩ — that is, y or z is fed directly from potentiometer wipers, and loading must be taken into account through the source resistance.

7.3 Operation as Divider

A multiplier connected as shown in Figure 7.4 operates as a divider. The following relationship holds:

y = x₂ / x₁

The denominator x₁ is subject to the constraint:

x₁ < 0

For a positive denominator, the divider does not operate stably.

The above relationship applies to normalized variables. In terms of voltages:

U_y / 10 V = (U_x₂ / 10 V) / (U_x₁ / 10 V) (U_x₁ < 0)

where U_x₁ and U_x₂ are the two input voltages and U_y is the output voltage.

[page 41: includes Fig. 7.4 — circuit diagram showing connection as divider, with inputs labeled x₁ and x₂, internal nodes X, Y, Z, and output Y.]

7.4 Operation as Square-Root Extractor

To generate a square-root relationship, the multiplier is connected as shown in Figure 7.5. The following relationship holds (in normalized variables):

y = √x (x > 0)

In terms of voltages:

U_y / 10 V = √(U_x / 10 V)

The corresponding characteristic curve for the square-root extractor is therefore as shown in Figure 7.6.

Note: Care must be taken that the output of the square-root extractor always remains positive. In the event that the circuit becomes overloaded during the course of the computation, a negative feedback resistance develops (x becomes negative), and the circuit becomes self-sustaining as a result of the overrange condition. In this case, the overrange between output and input must be resolved, or the additional diode circuit shown in Figure 7.7 must be used.

[page 42: includes Fig. 7.5 — circuit diagram showing connection as square-root extractor, with input x and output y; Fig. 7.6 — characteristic curve of the square-root extractor, showing the square-root curve shape.]

Page 43 — Figure with partial text

…the overrange at output and input must be resolved, or the additional diode circuit according to Figure 7.7 must be used.

[page 43: Fig. 7.7 — circuit diagram showing the square-root extractor with the additional protection diode connected between the output Y and the input stage, with inputs X, Y, Z labeled and the diode shown at the output.]

8. Potentiometer

8.1 Plug-In Connectors

Figure 8.1 shows the plug-in connectors of a potentiometer plug-in unit. Three freely accessible potentiometers and a fourth with a reference connection are available per plug-in unit. The potentiometer jacks are located between the potentiometer knobs.

Fig. 8.1: Plug-in connectors of the potentiometers

8.2 Setting

A potentiometer loaded according to Figure 8.2 with a total resistance R_G can be used to set a fraction α of the supply voltage U_0/U_1.

Fig. 8.2: Loaded potentiometer

[page 44: figure — three-column diagram of potentiometer plug-in connector positions; Fig. 8.1 caption below. Second figure shows the loaded potentiometer circuit symbol with voltage division, Fig. 8.2.]

The exact relationship is given by:

U_2 / U_1 = α / (1 + (R_L / R_G) · α · (1 − α))

The relative error is given by the following relationship:

F_rel = (U_2/U_1 − α) / α

F_rel = −(R_L / R_G) · α · (1 − α)

This relationship is illustrated by the curves shown in Figure 8.3.

Setting using correction curves

Under normal operating conditions, the standard load resistances for a potentiometer are: in the simplest case, only one single-pole setting can be made for the potentiometer at one-tenth of the voltage supply ratio (R_L/R_G = 0.1).

Figure 8.4 gives the difference values of the correction curves, which are to be taken as a higher potentiometer value than the ideal (unloaded) potentiometer characteristic. For a partial range setting, the circuit must be adjusted to α/2, and also with respect to the error, to (1 − α)/2.

[page 45: text continues on the relationship between loaded potentiometer setting and error; introduction of correction curves for adjustment using loaded potentiometers.]

Page 46 — Figure only

[page 46: figure only — Fig. 8.3: Four potentiometer configurations shown at top (cases 1–4, representing different standard-load situations with increasing number of potentiometer symbols). Below: a family of curves (labeled 1–4) plotted on a log-log graph. Horizontal axis: F_rel [%] from 10.0 down to 0.01. Vertical axis: x (normalized setting) from 0 to 1.0. The curves show the relationship between relative error F_rel and potentiometer setting x for the four standard loading cases.]

Page 47 — Figure only

[page 47: figure only — Fig. 8.4: Five potentiometer configurations shown at top (cases N₁ through N₅, representing different cascade or multi-pole loading configurations). Below: a family of curves labeled N₁–N₅ plotted similarly on a log-log graph. Horizontal axis: F_rel [%] (appears to span approximately 0.0001 to some upper bound). Vertical axis: x (normalized setting). Caption: “Fig. 8.4: Correction curves for analog computers.”]

Setting via Compensation Measurement

When the DO-80 voltmeter is used in the 100 mV range (position DIFF), Figure 8.5 shows the configuration of this voltmeter.

Fig. 8.5: Voltmeter configuration at 100 mV range (position DIFF)

For precise potentiometer setting, the following compensation circuit using an additional potentiometer is to be used:

Fig. 8.6: Compensation circuit

[page 48: Fig. 8.5 — block diagram showing the voltmeter connection with “grüne Buchse” (green jack) and “gelbe Buchse” (yellow jack) as inputs to an amplifier with gain shown, and a 4 mV output connection. Fig. 8.6 — compensation circuit diagram showing a +6 V reference supply, the potentiometer under test (Einzustellendes Potentiometer / potentiometer to be set), a reference potentiometer (Referenz-Potentiometer), and a −6 V supply rail feeding a null-detection voltmeter at the output.]

The setting procedure is carried out in the following steps:

Set the potentiometer under adjustment to + 10 V.
Connect the output of the potentiometer to the green voltmeter jack.
Set the reference potentiometer to − 10 V and connect its output also to the green voltmeter jack. This makes this potentiometer usable as a reference potentiometer.
Set the reference potentiometer according to the scale for the desired coefficient.
Adjust the potentiometer under setting until the voltmeter shows zero. This potentiometer is then set.

Setting with the aid of a digital voltmeter

The use of the compensation eliminates the need for the DO-80. Here, the output voltage of a potentiometer can be measured directly with sufficient accuracy.

[page 49: continuation of potentiometer setting procedure using digital voltmeter as the null detector in the compensation circuit.]

9. Comparators

9.1 Plug-In Connectors

Figure 9.1 shows the plug-in connectors of a comparator.

The letters E 1 and E 2 are the inputs of the comparator. The letters R 1 (short/abbreviated) and R 2 (short/abbreviated, cross-hatched) define the position of the downstream relay. The letter R (short, cross-hatched) defines a logical output of the comparator. RTR is a separately driven connection from the comparator output (see Section 9.2 for the exact mode of operation).

Fig. 9.1: Plug-in connectors of a comparator

9.2 Operation

Figure 9.2 shows schematically the circuit of the comparator and the meaning of the letters R and RTR.

[page 50: Fig. 9.1 — four-terminal connector diagram for comparator showing jacks labeled E1, E2, R1, R2, K, RTR in a row.]

Figure 9.2 shows the schematic circuit of the comparator and the meaning of the symbols R and RTR.

For the individual signals, the following truth table applies:

E1 + E2	RTR-Input	Relay position	Indicator lamp
> 0	open	0	off
> 0	1	1	on
< 0	1	1	on
< 0	0	1	on
< 0	1	1	on
= 0	0	0	off

It is evident that the logical comparator output K depends on the polarity of the sum of the input signals E1 and E2.

[page 51: Fig. 9.2 — schematic block diagram of the comparator, showing inputs E1 and E2 going through summing/amplifier stages, relay drivers (labeled SPULE / coil), with outputs to the relay contacts and indicator lamp. The truth table is reproduced below the figure.]

The relay controlled by the RTR must be able to be driven separately from the comparator, for example by a signal from a TTL flip-flop. The RTR input can also be driven by an external signal.

In the separately driven case, Figure 9.3 shows the activation of the function switch relay by the logical output K of the comparator.

Figure 9.3: Separate use of the comparator relay

Figure 9.4 shows the case of the reversed activation of the function-switch relay by the logical output K of the comparator.

Figure 9.4: Comparator with two cascaded relays

[page 52: Fig. 9.3 — circuit diagram showing the comparator relay driven separately via the logical output K, with a function-switch relay triggered by K. The diagram includes the comparator block and the downstream relay switching element. Fig. 9.4 — diagram showing a comparator with two cascaded relays connected to the function-switch relay.]

Note: The logical output K of a comparator can of course be used to drive all logic components with TTL specifications. In particular, the rear-panel jacks TAB, THT, and TDR can be driven directly.

[page 53: text only — note regarding the use of comparator logical output K with TTL logic components and rear-panel jacks TAB, THT, TDR.]

10. Function Switches

10.1 Plug-In Connectors

Each DO-80 can accommodate up to four function switches, which can be manually operated via pushbutton 22 (Figure 3.11). Figure 10.1 shows the plug-in connectors of a function switch in a potentiometer slot.

The rear-panel jacks HAND drive a logical output of the function switch. The relay can also be used as a comparator (Figure 9.2 [see Section 9.2]) to drive it. The position of the relay is determined by the state of the function switch. The state changes with each press of pushbutton 22.

Fig. 10.1: Plug-in connectors of a function switch

10.2 Operation

The internal structure of the function switch is identical to that of the comparator (Figure 9.2), with the difference that the input signal of the first amplifier is supplied from the front panel directly. In single operation, the following truth table applies:

[page 54: Fig. 10.1 — plug-in connector diagram for a function switch showing jack positions in a potentiometer slot. The truth table for single operation begins at the bottom of the page.]

10. Hand Switches (continued) — page 10-2

Hand switch	Lamp	RTR input	HAND output	Relay position
set	on	open	1	1
cleared	off	open	0	0
set	on	1	1	1
cleared	off	1	0	1
set	on	0	1	0
cleared	off	0	0	0

For supplying the RTR input with logical or analog signals, the information given in Section 9.2 applies.

Note: If several switches are to be actuated simultaneously, one switch must be pressed and held down while the other switches to be actuated are briefly pressed. When the first switch is released, all of the switch positions listed above are changed, and this can be followed on the corresponding indicator lamps.

11. Limiters

11.1 General

Each potentiometer plug-in unit contains the terminals of a limiter for bounding the output voltage of an amplifier (Fig. 11.1).

Fig. 11.1: Limiting of an amplifier — [graph showing a piecewise-linear transfer curve with clipping at levels A (positive) and B (negative)]

The trimmer potentiometers for stops A and B are located at the upper and lower edges of the patch-field panel respectively (see Fig. 11.2).

11.2 Operation as a Limiter

Fig. 11.2 shows the patch-field connections of a limiter. In order to produce a nonlinearity as shown in Fig. 11.1 (limiting), terminal A must be connected to the output and SP (summing point) of an amplifier, as Fig. 11.3 shows.

11. Limiters (continued) — page 11-2

Fig. 11.2: Patch-field connections of a limiter — [diagram showing the plug-in unit face with potentiometer B (positive limiting) at top, potentiometer A (negative limiting) at bottom, and terminals SP, A, and BEGR A]

In this configuration any amplifier whose summing point SP and output are connected to a limiter in accordance with Fig. 11.3 can be clamped to adjustable values. This applies in particular to integrators and open-loop (open) amplifiers. The latter, in combination with a limiter, yield a characteristic curve according to Fig. 11.4.

Fig. 11.3: Wiring of an amplifier with a limiter — [block diagram showing amplifier with SP and A terminals connected to the limiter, input X, output Y; plus a graph showing the resulting piecewise-linear characteristic with positive clamp at A and negative clamp at B]

11. Limiters (continued) — page 11-3

It should be pointed out that the limiting can be set to a positive and a negative stop independently of the level at which it is set. The positive stop must always be more positive than the negative stop.

Fig. 11.4: Limiter for open-loop amplifier — [graph of the clamped output characteristic showing flat regions at +A and −B flanking the linear region]

11.3 Simulation of Special Nonlinearities

With the limiters a number of special nonlinearities can be simulated. Numerous examples can be found in the literature; a few of them are reproduced below.

Triangular-wave Generation

Fig. 11.5: Circuit for triangular-wave generation using a limiter — [schematic with integrator and limiter in feedback loop producing a triangular output waveform]

11. Limiters (continued) — page 11-4

Fig. 11.6: Setting of the limiter in Fig. 11.5 — [graph showing the limiter transfer curve Y* vs. X, with the output clamped at +1 for positive input and linearly falling to −1 at X = 1, continuing below]

Signum Function

Fig. 11.7: Signum function — circuit and characteristic — [circuit diagram using an amplifier (gain 1, summing point SP) with a limiter in feedback (stop A set symmetrically), input X, output Y; corresponding step-function characteristic curve Y = sgn(X)]

11. Limiters (continued) — page 11-5

The limiter used in the circuit of Fig. 11.8 must be set according to Fig. 11.9.

Dead Zone

Fig. 11.8: Dead zone — circuit and characteristic — [circuit diagram: input X feeds a limiter (with SP) whose output is subtracted from the input via a summing amplifier to produce Y; characteristic shows dead zone between −A and −B on the X-axis with unit-slope lines outside]

Fig. 11.9: Setting of the limiter in Fig. 11.8 — [transfer curve of the limiter showing output A on the positive side and output B on the negative side, with horizontal (zero) region in between, used to generate the dead-zone transfer function]

11. Limiters (continued) — page 11-6

Rectangular Hysteresis (Relay Characteristic)

Fig. 11.10: Rectangular hysteresis — circuit and characteristic — [schematic: input X drives an amplifier whose output passes through a limiter (stops A, B) and is fed back via a coefficient multiplier K; the resulting characteristic shows a rectangular hysteresis loop with switching points at b = K·A and a = K·B; output Y takes values +A and −B]

The limiter used in the circuit of Fig. 11.10 must be set according to Fig. 11.11.

Fig. 11.11: Setting of the limiter in Fig. 9.10 — [limiter transfer curve showing output +A for positive input and output −B for negative input, with the switching occurring near zero; X_B marks the breakpoint on the abscissa]

11. Limiters (continued) — page 11-7

Three-Point Hysteresis

Fig. 11.12: Three-point hysteresis — circuit and characteristic — [circuit diagram with two parallel limiter paths: upper limiter (stop A) fed from −1 constant and X, lower limiter (stop B) fed from +1 constant and X; outputs Y_B1 and Y_B2 combined via coefficient multiplier K into a summing amplifier giving Y; characteristic curve shows a five-segment staircase with outer plateaus at ±A and inner levels at ±b, with switching points at ±C and ±D on the X-axis; relations a = K·A and b = K·B]

12. Variable Diode Function Generator

12.1 General

Fig. 12.1 shows the patch-field connections of a function-generator plug-in unit.

Fig. 12.1: Patch-field connections of a function-generator plug-in unit — [annotated diagram of the plug-in panel face, labeling three groups of jacks:

Upper function generator (e.g. Sine/Cosine): terminals numbered 0 through +7
Middle (linear) function generator: terminals 0 through +4 (or similar)
Lower function generator (e.g. −Y_1·Y_2): terminals numbered 0 through +7
Input/output potentiometer for upper function generator (right side)
Input/output potentiometer for lower function generator (right side)
Parallel connection bus
Derivation terminal]

12. Variable Diode Function Generator (continued) — page 12-2

One plug-in unit contains two adjustable function generators, each with equidistant breakpoints.

The upper function generator has 2 × 5 = 10 breakpoints (Fig. 12.2); the lower one has 2 × 4 = 8 breakpoints (Fig. 12.3).

Fig. 12.2: Breakpoints of the upper function generator — [graph of Y* vs. X (in Volt) showing 10 equidistant breakpoints spanning −5 to +5 V]

Fig. 12.3: Breakpoints of the lower function generator — [graph of Y* vs. X (in Volt) showing 8 equidistant breakpoints spanning −4 to +4 V]

Using the breakpoints, any desired arbitrary function can be approximated in all four quadrants by a polygon. With 18 polygon segments a total of 18 polygon segments are available between −10 Volt and +10 Volt.

Fig. 12.4: Example of a function approximated by a polygon — [graph showing a smooth bell-shaped function together with its piecewise-linear (polygon) approximation, demonstrating the approximation quality]

12. Variable Diode Function Generator (continued) — page 12-3

On the front panel of the plug-in unit there are potentiometers that are accessible from the front, with which the slope of the individual segments can be set.

For the simulation of complicated functions both function generators can be switched in parallel. A total of 18 polygon segments are thus available between −10 Volt and +10 Volt.

12.2 Structure of the Function-Generator Plug-in Unit

Fig. 12.5 shows the schematic structure of a function generator contained in one plug-in unit.

Fig. 12.5: Schematic representation of a function-generator plug-in unit — [block diagram showing: input X fed to two parallel networks — an upper function-generator network (Funktionsgeber-Netzwerk) and a lower function-generator network — each followed by a summing amplifier (Polygonzug-Verstärker), with outputs combined in a final output amplifier; the Steilheitspotentiometer (slope potentiometers) and additional inputs are also indicated]

12. Variable Diode Function Generator (continued) — page 12-4

The lower function generator is pre-set for parallel operation with a relay that places it into the parallel connection mode, and its output amplifier has furthermore a quadratic input (of the form Y = f(x)·x), so that operations of the form

Z = f(x) · x

are possible.

In addition to the two variable function generators the plug-in unit also contains a fixed nonlinear function (Signum function, Dead Zone, etc.).

12.3 Setting a Function Generator

In principle two procedures can be distinguished for setting a function generator:

12.3.1 Setting with the Aid of an Oscilloscope

This method requires the least time and additionally yields the greatest accuracy. It does, however, require the use of a high-quality oscilloscope.

The following circuit is constructed:

[Block diagram: signal source → DO 80 function generator → output Y; the DO 80 operates in repetitive (Repetier) mode at 10 ms compute / 10 ms pause cycle, and the oscilloscope displays the resulting function curve]

The DO 80 is operated in repetitive mode with 10 ms compute and 10 ms pause intervals. In this way a stationary image of the set function appears on the oscilloscope screen.

12. Variable Diode Function Generator (continued) — page 12-5

First, with the aid of the Y_0 potentiometer of the function generator, the value f(x = 0) is set (verify the value at the Stützstelle x = 0).

For setting the individual slopes the following procedure is used:

x = 0 is set. With Y_0-potentiometer set the value f(x = 0).
x = s_1 (1 Volt) is set. With the Y_1 potentiometer set the value f(s_1).
x = s_1 (1 Volt) is set. With Y_{1,a} potentiometer set the value f(s_1).
x = s_2 (3 Volt) is set. With the Y_2 potentiometer set the value f(s_2).
The same procedure is repeated for each further breakpoint. At each step the Steilheitspotentiometer is advanced to the next breakpoint and adjusted accordingly.
After setting the function at x = 0, the settings are carried out for all breakpoints s_{j} (−1 Volt). The curve setting begins with the breakpoint x_{j} = −1 Volt.

The curve must be set starting from the innermost breakpoints and working outward.

After an initial setting, the displayed function may already be satisfactory. In certain cases it may be necessary to repeat the setting procedure; however, no more than two to three repetitions are required.

12.3.2 Setting with the Aid of a DC Voltmeter

This setting is the more precise one, although it takes somewhat more time. However, it has the advantage that the setting can take place while computations are being observed.

The procedure consists of the following two basic steps:

Function f(x) is constructed on millimeter-ruled paper.
The setting is performed using a DC voltmeter (Gleichspannungs-Schreiber).

[Block diagram: input x → function generator f(x) → output; output connected to a DC voltmeter/recorder (Gleichspannungs-Schreiber)]

12. Variable Diode Function Generator (continued) — page 12-6

x = 0 is set. With the y_0-potentiometer set the value f(x = 0).
x = s_1 (1 Volt) is set. With Y_{1,a} potentiometer set the value f(s_1).
x = s_2 (3 Volt) is set. With the Steilheitspotentiometer set the value f(s_2) at step 1 in the same manner.
x = s_3 (3 Volt) is set. With the Steilheitspotentiometer set the value f(s_3).
After setting each breakpoint at x = 0, the procedure for the remaining positive breakpoints is continued. The curve setting is performed starting from the innermost breakpoints (s_1, s_2, …) outward.

The advantage of setting with a DC voltmeter is the possibility of observing the individual breakpoints more closely than with an oscilloscope. However, this method is somewhat slower than the oscilloscope method.

12.4 Parallel Operation of Function Generators

For the simulation of more complex functions, both function generators in the plug-in unit can be connected in parallel. For this purpose, terminal F on the plug-in unit is connected to the terminal defined alongside it (Fig. 12.6).

Fig. 12.6: Parallel connection — [diagram of the plug-in unit patch panel showing the F terminal and the associated jumper connection point, with labels for the equidistant breakpoints of both upper and lower function generators]

Internally, connecting the two function generators in parallel routes through the upper generator network for the equidistant breakpoints.

The function generator at position x = 0 is connected to the y_0-potentiometer of the upper function generator.

12. Variable Diode Function Generator (continued) — page 12-7

Fig. 12.7 shows schematically the wiring of the function generators in parallel operation.

Fig. 12.7: Schematic representation of parallel operation — [block diagram showing two function-generator networks (upper and lower) with their respective Steilheitspotentiometer banks combined into a single summing amplifier and then a final output amplifier; the combined output Y is available at the patch panel; a constant −1 is supplied at the input of the upper network]

In parallel operation the function generator can be used for more complex and arbitrary functions. The y_0 potentiometer for the DC offset (Einspeisung) is provided by the lower function generator, and the Y_p potentiometer of the lower function generator is available for setting.

The setting of the two parallel-connected function generators follows the procedure described in section 12.3, with the individual steps carried out in the following order: + 1 (upper function generator), + 2 (lower function generator), + 3 (upper function generator), and so on. If necessary, the setting can also be repeated.

12. Variable Diode Function Generator (continued) — page 12-8

12.5 Fixed Function Generator (Diode Array)

The upper section of the patch panel also provides fixed function generators with three connections:

E 1 and E 2: input and output
E 2: direction (sign, arbitrary)
Control variable

Both E 1 and E 2 connections carry the same signal; the signal flow is from E 1 to E 2 or can be reversed. For realization the function is set up using a comparator with summing point SP.

In the following sections several functions that can be simulated with this fixed function generator are described.

Signum Function

Fig. 12.8: Simulation of a signum function — [block diagram: input signal x feeds an operational amplifier; the antiparallel diodes in the feedback path of the amplifier produce the signum nonlinearity; output is labelled F; comparator output SP with associated fixed network]

The diodes at the control input provide a step response (Ordnungssprung). The antiparallel diodes in the return path of the amplifier establish the signum function. An offset of approximately 0.5 Volt exists between the control variable x and the actually achieved switching threshold.

12. Variable Diode Function Generator (continued) — page 12-9 / 12-10

Dead Zone

Fig. 12.9: Simulation of a dead zone — [circuit diagram: input X feeds antiparallel diodes (symbol shown), then through a 10 kΩ resistor and a 100 kΩ feedback resistor into an inverting amplifier; the amplifier has terminals SP, E1, E2, and S (for the width control variable z); a second path with resistors 100 kΩ and 10 kΩ sets the lower branch; output Y; below, the associated characteristic: Y vs. X showing the dead zone of total width 2z centred at the origin, with unity slope outside; annotation “Slope 1 (Steigung 1)”]

The width 2z of the dead zone is achieved exactly only with the aid of the antiparallel diodes. Without these diodes an error of approximately 0.5 Volt arises between the control variable z and the half-width of the dead zone.

12 – 11 (page 73)

Three-Point Nonlinearity

Figure 12.10: Implementation of a three-point nonlinearity

Inputs A and B are set using the trim potentiometers of the limiter. The width Z corresponds to the control variable S, set using the anti-parallel diode circuit. Without this circuit, Z produces an error of approximately 0.5 V. Because the limiter allows the setting of two breakpoints in the upper and lower half-planes, it is possible to realize nonlinearities up to figure 12.11 as special cases according to figure 12.10.

12 – 12 (page 74)

Figure 12.11: Special cases of the circuit shown in figure 12.10

[page 74: figure only — two X/Y diagrams showing special cases of the three-point nonlinearity circuit. Left diagram: step function with amplitude A and width Z above the X-axis, offset B below. Right diagram: negative step with amplitude A and offset B below the X-axis, with deadzone Z.]

13 – 1 (page 75)

13. Logic Components

13.1 General

The DO 80 can be fitted internally with up to 16 plug-in modules that accommodate analog logic components:

One module with a single 4-bit counter and two flip-flops
One module with five flip-flops and one monoflop
One module with five AND/NAND gates

When logic components are inserted for the first time through the operator panel, the logic inputs and outputs must be connected on the right-hand side of the respective board — the takt (clock) input is connected on the left-hand side of the board, and the analog interconnect board can also be accessed on both sides (see section 12.10).

The logic components are implemented in TTL technology and operate within the following voltage levels:

“0”: 0 V to 0.4 V → Logic “0”
“1”: 2.4 V to 5 V → Logic “1”

All inputs and outputs are diode-protected against negative voltages as well as against voltages above 5 V. All components are equipped with special output stages, so that the TTL signal can also be passed directly to the analog section, where an integrator can directly process it as a step input.

13 – 2 (page 76)

In particular, parallel connection of outputs is also possible to form a “wired AND” or a “wired OR.”

Output drive capability: 10 logic inputs or 2 relays

13.2 Clock Module

Figure 13.1: Clock module (patch panel)

[page 76: figure showing the patch panel layout of the clock module, with two counters (Zähler 1 and Zähler 2), each with connections labeled T, RS, Z1/Z2, and binary-weighted outputs 1, 2, 4, 8; also a control panel (Steuerfeld) section at the bottom with ST, R, H, and RS connections.]

13 – 3 (page 77)

Figure 13.1 shows the patch panel of a clock module. In addition to the inputs and outputs shown, there are also two groups of four light-emitting diodes for displaying the states of the two counter stages.

13.2.1 Clock Generator

Figure 13.2 shows the principle of construction of the clock generator.

Figure 13.2: Principle circuit diagram of the clock generator

[page 77: block diagram showing an oscillator followed by a chain of four T/10 frequency dividers (÷10 stages), with outputs tapped after each divider stage.]

The clock generator consists of a 10 kHz oscillator whose output frequency can be divided by a factor of up to 1 by using the T/10 divider stages. Each individual T/10 stage divides the frequency by a further factor of 10. The individual T/10 stages deliver pulses at the following frequencies:

Output	T/10 stages not pressed	T/10 stages pressed
0 (× 10⁰)	1 Hz	10 kHz
1 (× 10¹)	10 Hz	1 kHz
2 (× 10²)	100 Hz	100 Hz
3 (× 10³)	1 kHz	10 Hz

13 – 4 (page 78)

The clock pulses have a mark-to-space ratio of 1:9, so that direct observation on the oscilloscope is made easier, especially at lower frequencies.

The operating modes of the clock generator are controlled by pushbuttons B and R in the control panel. The individual pushbuttons correspond to the following operating modes:

B	R	Operating mode
0	0	Clock generator in IC (initial condition)
1	0	Clock generator in AC (run condition)
0	1	Clock generator operating
0	0	Clock generator operating but held (paused) when Monoflop is in IC

In normal operation, the pushbuttons B and R are connected with the corresponding wired pushbuttons AB, IN, and GT so that the clock generator is switched between the two operating modes together with the analog computing section.

In this case, the clock generator connects with the dedicated AB, IN, and GT pushbuttons of the control bus.

13 – 5 (page 79)

13.2.2 4-Bit Counter

Figure 13.4 shows schematically the construction of a 4-bit counter.

Figure 13.4: Principle circuit diagram of the counter

[page 79: block diagram of a 4-bit counter with clock input T and outputs Q (4 bits), with a reset input RS and a carry/overflow output Z.]

The counter is designed as a binary forward counter. The individual connections have the following functions:

T — Clock input: with each negative-going (falling) edge at this input, the counter state is incremented by “1” (indicated by the display lighting up).
RS — Reset input: a positive (rising) edge at this input resets the counter state to zero and blocks it for approximately 3 µs.
R — Control input: connected with the control variable R of the clock generator. A logic “1” at this input causes the counter to reset and remain blocked when the R key is pressed.

13 – 6 (page 80)

…resets the counter and holds it blocked (inhibited).

If the control variable R is as shown in figure 13.3 (normally connected to AB and IN of the control panel), then the counter is set to zero and held at that state during IC operation.

It counts further only when the Potentiometer R input becomes inactive. The state of each output corresponds to the following truth table:

Output	Significance
1	Least Significant Bit 1 (weight 1)
2	Bit 2 (weight 2)
4	Bit 4 (weight 4)
8	Most Significant Bit 8 (weight 8)

The outputs drive light-emitting diodes (LEDs). A lit LED indicates that the corresponding output is at logic “1.”

The states of the individual outputs follow this truth table:

Number of T-pulses vs. outputs:

Count	8	4	2	1
0	0	0	0	0
1	0	0	0	1
2	0	0	1	0
3	0	0	1	1
4	0	1	0	0
5	0	1	0	1
6	0	1	1	0
7	0	1	1	1
8	1	0	0	0
9	1	0	0	1
10	1	0	1	0
11	1	0	1	1
12	1	1	0	0
13	1	1	0	1
14	1	1	1	0
15	1	1	1	1

13 – 7 (page 81)

The counter thus counts from 0 to 15 impulses and then rolls back to zero from the 16th impulse onward.

13.2.3 Application example: Expansion beyond 4 bits

If more than 15 pulses are to be counted, two or more counters must be cascaded. Output Z of the first counter is connected to the T input of the second counter (figure 13.5).

Figure 13.5: Cascading two counters

[page 81: block diagram showing two counter modules (Zähler 1 and Zähler 2) connected in series; the overflow output Z of Zähler 1 feeds the T input of Zähler 2, with binary outputs shown from both stages.]

When two counters are used, up to 255 pulses can be counted (corresponding to 8 bits). For this application the following truth table applies:

Count	Outputs Zähler 2	Outputs Zähler 1
	8	4
1	0	0
…
14	0	0
15	0	0
16	0	0
…
254	1	1
255	1	1

13 – 8 (page 82)

Programming as a Decade Counter

Each counter can optionally be pre-loaded from a decimal value using the Zähleingang (counter input). This works as follows: the Zählerstand (counter state) can be preset once using the RS input, so that outputs 8, 4 and 2 are used to preset the count accordingly (wired OR).

Example: 11 pulses at input T → the state is set (decimal) to the corresponding value:

8	4	2	1	Z
0	0	0	0	0

Thus bits 8, 4, 2 and 1 are to be interconnected in the corresponding way (figure 13.6).

Figure 13.6: Programming as a decade counter

[page 82: block diagram of the 4-bit counter with outputs 8, 4, 2, 1 and the Z carry output; the outputs 2 and 4 are connected back via OR logic to the RS input, creating a modulo-5 (or modulo-10, depending on wiring) counter reset.]

On the rising edge at T, an impulse is triggered at output Z until counter state Z = 0, which is then reset.

Automatic Reset When a Pre-set Count Is Reached

If the counter is to automatically reset itself to the start value (initial condition), output Z (figure 13.6) should be connected to the RS input of the same counter, as follows:

13 – 9 (page 83)

Example: After every 5 clock impulses the counter should emit one pulse.

Figure 13.7: Automatic reset at counter state 5

[page 83: diagram showing the counter with T clock input and outputs 1, 2, 4, 8, with outputs 1 and 4 (binary 5) connected back to the RS reset input, and Z as the carry output. Below, a timing diagram showing: T — regular pulse train; Z — single output pulse for each group of 5 T pulses; Zählerstand (counter state) — cycles 0, 1, 2, 3, 4, 0, 1, 2, 3, 4, 0 …]

13 – 10 (page 84)

13.3 Flip-Flop Module

Figure 13.8: Flip-flop module (patch panel)

[page 84: diagram of the flip-flop module patch panel showing three RS flip-flop sections (each with inputs S, R and output F, as well as an inverted output F̄) and one monoflop section with inputs T, C, R and output M; a control panel (Steuerfeld) section at the bottom with R and RS inputs.]

Figure 13.8 shows the patch panel of a flip-flop module, which contains three RS flip-flops and one monoflop. In the flip-flop areas there are LED indicators for the respective flip-flop state. In the monoflop area, the pulse duration of the monoflop can be adjusted using a potentiometer.

13 – 11 (page 85)

13.3.1 Flip-Flops

The flip-flops are implemented as RS flip-flops. The principle circuit diagram is shown in figure 13.9.

Figure 13.9: Principle circuit diagram of a single flip-flop

[page 85: block diagram showing an RS flip-flop with inputs S, R and outputs F (true), F̄ (inverted), with a T clock input and a Steuereingang (control input) labelled P.]

The connections have the following functions:

S — Set input: a logic “0” at this input sets the flip-flop to state F = 1 (the LED indicator lights up).
R — Reset input: a logic “0” at this input resets the flip-flop to state F = 0 (the LED indicator does not light up).
T — Clock input: with each negative-going (falling) edge at this input, the flip-flop adopts its new state.
F, F̄ — True and inverted output.
P, P̄ — Control input for the flip-flop state control.

The behavior of the S and R inputs is described by the following truth table:

S	R	F	F̄	Note
1	0	1	0
0	1	0	1
0	0	—	—	(no valid condition, indeterminate) — therefore invalid!

13 – 12 (page 86)

The precondition for the function of the S and R inputs is that the control input P is at logic “1” — i.e., that state P = 1 is signaled.

The clock input T is effective when it delivers a logic “0” at P. When P = 0, the flip-flop is set; when P = 1, the flip-flop is cleared (reset) to zero (open).

The control input R in the lower control bus area operates as follows: when the control variable R is at logic “0,” all three flip-flops are reset to their zero states and blocked. In normal operation, the pushbutton R is connected with the wired pushbutton buses AB, IN, and GT so that the flip-flops are switched in coordination with the analog computing section.

Note: The control bus R in the flip-flop module is NOT identical with the control bus RS of the clock module.

13.3.2 Monoflop

Figure 13.10 shows the principle circuit diagram of a monoflop.

Figure 13.10: Principle circuit diagram of a monoflop

[page 86: block diagram of the monoflop circuit with trigger input T, timing capacitor connection C, reset input R, and output M.]

13 – 13 (page 87)

The connections have the following meaning:

T — Trigger input: a positive (rising) edge allows the output M to remain at logic “1” for a defined, adjustable period.
M — Output.
C — Connection for an external timing capacitor to extend the pulse duration (standard value).

Potentiometer: Setting of the pulse duration.

The adjustable range with the internal potentiometer is approximately ca. 0.5 ms to 1 ms. With the addition of external capacitors, the pulse duration can be extended as follows:

External capacitor	Maximum pulse duration
10 nF	2 ms
100 nF	10 ms
1 µF	100 ms
10 µF	1 sec

Note: the accuracy of the monoflop depends on the quality (tolerance) of the capacitor — approximately 0.5 µF/unit.

The monoflop behaves with respect to the control input R in the same way as the flip-flops — for example, when R = 0 the monoflop is blocked.

13 – 14 (page 88)

13.4 Gate Module

Figure 13.11: Gate module (patch panel)

[page 88: diagram of the gate module patch panel showing five AND/NAND gate symbols, each with two inputs (A₁, A₂) and two outputs (B, B̄); five identical gate sections stacked vertically.]

Figure 13.11 shows the patch panel layout of the gate module.

13 – 15 (page 89)

One module contains five AND/NAND gates with a function described by the following truth table:

A₁	A₂	B	B̄
0	0	0	1
0	1	0	1
1	0	0	1
1	1	1	0

Expansion of the number of inputs is possible by connecting the outputs of several gates in parallel (figure 13.12).

Figure 13.12: Expansion to an AND gate with 4 inputs

[page 89: schematic showing two 2-input AND/NAND gates with inputs A₁, A₂ and A₃, A₄ respectively; outputs connected together to realize: B = A₁ ∧ A₂ ∧ A₃ ∧ A₄]

14 – 1 (page 90)

14. Function Generator

14.1 General

The function generator serves to reproduce (simulate) track functions; in the context of repetitive analog computing, it also serves to reproduce the transfer function.

The function is:

F = f^(ΔPS)

The simulation of arbitrary functions is realized with all amplitude ranges by the DO 80 as a piecewise linear (step) approximation of the function.

The function generator is a single plug-in module that is installed on each DO 80 cabinet. The single circuit consists only of a right-hand and left-hand (not right and left) Totzeitleid (dead-time element/function), which through positional adjustment through the analog computing section is described as follows.

Both as an analog computing module, as well as a Taktgeber (clock) module, these boards are installed on both the right-hand and left-hand side of the cabinet (cabinet frames), with the positional adjustments through the analog computing section.

The function generator provides logic signals according to the requirements of sections 13 to 13. Both of these signals are generated from a TTL-Signal-Schaltkreis.

The timing signal passes through according to the principle circuit diagram in figure 14.1.

Figure 14.1: Principle circuit diagram of the function generator

[page 90: block diagram showing the function generator consisting of: input (Eingang) → A/D converter (A/D-Wandler) → memory/register (Speicher) with control → D/A converter (D/A-Wandler) → output (Ausgang); labeled “memory” (Speicher) and “control” (Schaltstufe = switching stage).]

14 — Sampling Module (Track-and-Hold / SHA)

Page 91 (14 – 2)

The input voltage U_E is digitized by an 8-bit A/D converter and fed into a shift register of 100 words at 8 bits each. After 100 shift pulses the analog equivalent of the stored value reappears at the output of the D/A converter and is fed back to the output as an analog voltage. The frequency of the shift pulses thus determines the delay time of the module.

14.2 Stacked-Field Modules

[page 91: block diagram figure — Bild 14.2: Stacked-Field Modules]

The figure shows a stacked-field module with the following labeled connections:

Eingänge (Inputs) — two input terminals at the bottom left
Ausgang (Output) — output terminal at the top right
Eingang des Spannungs-/Frequenz-Wandlers (Input of the voltage/frequency converter)
Ausgang des Spannungs-/Frequenz-Wandlers (Output of the voltage/frequency converter)
Eingang für Schreib- und Wandlertakt (Input for write and converter clock)
Steuerbereich für Betriebsart (Control area for operating mode)
Steuerbereich nicht verwendet (Control area not used)
Steuerfeld für Betriebsarten (Control panel for operating modes)

Page 92 (14 – 3)

Figure 14.2 shows the stacked-field module of the TAKT-Eingang board. In the upper section the diagram also shows photocouplers/diodes that are used, for example, as special digitalizer circuits or in connection with TEKO boards as fast function generators.

14.3 Operation of the TAKT Module

This section describes the operation of the TAKT module.

The TAKT-Eingang feeds an analog sampled signal as the input to the A/D converter and transmits the analog signal after conversion to the D/A converter. The TAKT module passes the analog signal from any previously sampled value over the D/A converter. The output frequency of the voltage/frequency converter depends on the settings of the a/b buttons (left side of the a/b-Wandler). The TAKT module is an analog voltage processed correspondingly and is fed from the D/A converter further to the shift register.

The output frequency of the voltage/frequency converter depends on the setting of the T/D test performed through the a/b buttons (instead of the D/A-button). The control of the voltage/frequency converter is accomplished via inputs B and N.

With RING control, each button of the D/A-button (input B and N at positions 1 and 10) is available.

Above this, the RING specially controls the output of the shift register to step 1 and 10 of the shift register register. Thus the D/A converter triggers the shift register outputs of the converter and shift register module in synchrony.

Page 93 (14 – 4)

[page 93: figure only — Block diagram of the stacked-field module (Bild 14.3)]

The block diagram shows the following functional blocks connected in sequence:

Eingänge (Inputs) — two input summing amplifiers (triangular symbols) at the bottom
A/D-Wandler (A/D Converter) — receives signals from the input amplifiers
Schieberegister (Shift Register) — 100-word × 8-bit shift register, connected to A/D converter (input at bottom labeled “8”) and providing output (top labeled “8”) and count input (labeled “100”)
Steuerung (Control logic) — interconnects the shift register, voltage/frequency converter, and operating-mode inputs
Spannungs-/Frequenz-Wandler (Voltage/Frequency Converter) — on the right, with its own control inputs (labeled U_S and f_B)
D/A-Wandler (D/A Converter) — receives the 8-bit output from the shift register
Output amplifier (triangular symbol) leading to Ausgang (Output) at the top

Control inputs labeled on the right side: B, N, f_B (frequency input), and U_S (voltage input). The control block connects to operating-mode buttons AB, DN, HT.

Page 94 (14 – 5)

14.4 Adjustment Range of the Voltage/Frequency Converter

The relationship between the input voltage U_E and the frequency of the output signal is linear:

f = a · U_E

The individual adjustment steps are given in the following table:

Taste (Key) V/10	Überbrückung (Bypass) a1, a10	a	for U_E = −0.1 V	to +10 V
not pressed	a1	100 Hz/V	10 Hz bis 1 kHz	10 Hz bis 100 ms
pressed	a1	1 kHz/V	100 Hz bis 10 kHz	1 Hz bis 10 ms
not pressed	a10	2 kHz/V	100 Hz bis 50 kHz	1 s bis 10 ms
pressed	a10	10 kHz/V	1 kHz bis 100 kHz	1 ms bis 1 ms

Note: The voltage/frequency converter operates only for positive input voltages U_E. The output frequency f_A and the total time T_G satisfy the following relationship:

f_A = (100 / T_G) · U_E

Page 95 (14 – 6)

14.5 Operating Mode Control

The operating mode control of the voltage/frequency converter is accomplished via inputs B and N.

Figure 14.4 shows the connection of inputs B and N with the two toggle switches DN and HT. Via the toggle switches AB, DN, and HT, three operating modes of the TAKT module can be set.

Bild 14.4: Normal-beschaltung des Steuerfeldes (Normal wiring of the control panel)

Schalterstellung (Switch position)	B	N	Betriebsart des Taktgliedes (Operating mode of the TAKT module)
AB	1	1	AB
DN	1	0	DN
HT	0	0	HT

Notes on operating modes:

DN: The voltage/frequency converter operates according to the normal equation (runs freely). It is in the Normalbetrieb (normal operation) state and populates the Taktglied content.
HT: The converter is in the Hold state and samples the instantaneous content of the shift register without change. The delay time of the register is thus independent of which part (converter or shift register) of the converter and shift register module will be triggered.
AB: After the transition to operating mode AB, a special frequency generator for 1 ms to 100 kHz runs as the input signal. Simultaneously this is applied to the input of the shift register. The content of the shift register is thereby clocked at 1 ms intervals. Thus the total time of the shift register is exactly equal to 1 s of the converter and shift register section that will be triggered.

Page 96 (14 – 7)

A special frequency generator for 1 ms to 100 kHz is used as the input signal. Simultaneously this is applied to the input of the shift register. The content of the shift register is thereby updated at 1 ms intervals. Thus the total time of the shift register is exactly 1 s, independent of which part of the converter and shift register module will be triggered.

14.6 Single-Step Register Operation

By pressing both of the RING-designated buttons simultaneously, the input to the D/A converter is disconnected (see Bild 14.3) and connected instead to the current content of the shift register. The momentary content of the shift register can therefore be read out and used. This results in an output corresponding to the converter and shift register output. Thus the total time can be used as a function generator.

The common content of the shift register is output cyclically in accordance with the converter and shift register specification. Thus the total time can be used as a function generator.

Count	8	4	2	1
0	0	0	0	0
1	0	0	0	1
2	0	0	1	0
3	0	0	1	1
4	0	1	0	0
5	0	1	0	1
6	0	1	1	0
7	0	1	1	1
8	1	0	0	0
9	1	0	0	1
10	1	0	1	0
11	1	0	1	1
12	1	1	0	0
13	1	1	0	1
14	1	1	1	0
15	1	1	1	1

Count	8	4	2	1
0	0	0	0	0
1	0	0	0	1
2	0	0	1	0
3	0	0	1	1
4	0	1	0	0
5	0	1	0	1
6	0	1	1	0
7	0	1	1	1
8	1	0	0	0
9	1	0	0	1
10	1	0	1	0
11	1	0	1	1
12	1	1	0	0
13	1	1	0	1
14	1	1	1	0
15	1	1	1	1

Count	8	4	2	1
0	0	0	0	0
1	0	0	0	1
2	0	0	1	0
3	0	0	1	1
4	0	1	0	0
5	0	1	0	1
6	0	1	1	0
7	0	1	1	1
8	1	0	0	0
9	1	0	0	1
10	1	0	1	0
11	1	0	1	1
12	1	1	0	0
13	1	1	0	1
14	1	1	1	0
15	1	1	1	1