Beschreibung des Digitalzusatzes DEX 802

Complete English translation of the original German-language document (67 pages).

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Description of the Digital Extension DEX

Table of Contents

Section	Page
1. Function and Purpose of the DEX	4
2. List of Abbreviations Used	4
3. Technical Overview	6
3.1 Mechanical Construction	6
3.2 Technical Data	7
4. Bedienungsanleitung (Operating Instructions)	9
4.1 Notes on Handling the Digital Elements	9
4.2 Description of the Digital Programming Field (DPF)	9
4.3 Controls and Operating Elements	10
4.4 Overall Listing of the Buses of the DEX	11
4.4.1 Individual Element Descriptions	14
4.4.1.1 Alphabetical Listing of the Buses of the DEX (continuation)	—
5. Description of the Exchangeable Elements of the DEX	—
6. Overall View of Housings and Control Panels	—
6.1 Housing	—
6.2 Control Panel and Inputs	—
6.3 Control Panel and Outputs	—
6.3.1 Output Lines	—
6.3.2 Interconnect Bus	—
6.4 Integrator Clock (DBG)	—
6.4.1 Free Takt (clock)	—
6.4.1.1 Selector Switch	—
6.4.1.2 Time Base	—
6.4.1.3 Set Time of Day 1	—
6.4.1.4 Set Time of Day 2	—
6.4.1.5 End of Calculation Cycle	—
6.4.1.6 Calculation Cycle Repetition	—
6.4.2 Calculation Cycle Signal — Hold	—
6.5 Timing of the Integrator Trigger Contacts	—
6.5.1 Outputs of the Comparator Amplifiers, Main Calculator	36
6.5.2 Outputs of the Comparator Amplifiers in Automatic Mode	37
6.5.3 Outputs of the Comparator Amplifiers, External Operation	—
6.5.3A Outputs of the Comparator Amplifiers, Bus	—
6.5.3B I/O — External Bus	—
6.6 DEX Control Switches (Schaltglieder)	—
6.6.1 Overview of the Integrator Switches	—
6.6.1.1 Selector Switches, Type I	—
6.6.1.2 Entry Fields	—
6.6.1.3 Function Switch	38
6.6.1.3.1 Interleaved Contacts	—
6.6.2 Selector Switches, Dual Bus	—
6.6.2.1 Contacts	—
6.6.3 Switching Grid (Schaltgitter)	—
6.7 Interrupt — Inputs	—
6.7.1 Contol Lines	—
6.8 Integrator — Status Lines	—
6.9 Crossover	—
6.9.1 Distributor Clk	—
6.10 Integrators Clk	42
6.10.1 Start Integrator	43
6.11 Takt Clk	—
6.11.1 Reset Pulse Distributor	—
6.12 Interrupt Line	—
6.13 CMOS — Inputs	—
6.13.1 CMOS	—
6.13.2 CMOS Clocking	—
6.14 Reset Interrupt — Outputs	—
6.15 Interrupt — Outputs	—
6.15.1 Befehl (Command)	46

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(Page 2 — continuation of Table of Contents)

Section	Page
6.5.4 Weiter-Befehl (Continue Command)	26
6.5.5 Haltezeit Ende (End of Hold Time)	27
6.5.5.1 Ende der Haltezeit 1	—
6.5.5.2 Ende der Haltezeit 2	—
6.5.5.3 Ende der Haltezeit	—
6.5.6 Start eines neuen Rechenzyklus (Start of a New Computation Cycle)	28
6.5.7 Rechnungszyklussignal — Sperre	33
6.5.8 Zeitgebersteuerung der Zeitgebertaktes	35
6.4.1 Ausgange der Komparatorverstärker, Hauptrechner	36
6.4.2 Ausgange der Komparatorverstärker im Automatikprogramm	37
6.4.3 Buttons and Betriebsarten	37
6.4.5 Alphabetisches Verzeichnis der Buchsen des DEX	11

7. Description of the Interchangeable Elements of the DEX	—
7.1 Inverter (INV)	48
7.2 NAND 2	49
7.3 NAND 4	—
7.4 NOR 2	51
7.5 NOR 4	52
7.6 Flipflop (FF)	53
7.7 Schieberegister (SR)	55
7.8 Zähler (Z)	57
7.9 Handling (HV)	59

8. Description of the Housings and Control Panels	—
8.1 Housings	64
8.2 Inputs and Outputs	64
8.3 Control Panels and Other Outputs	65
8.4 Comparison of the Housings and Control Panels	66

| Appendix 1: Circuit diagram for the control panels | — | | Appendix 2: Layout of the Digital Program Fields | — | | Appendix 3: Interconnection plan Interface — Analog computer | — |

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1. Function and Purpose of the DEX

The digital extension DEX is a component of the hybrid computing system.

Freely programmable digital elements enable any desired combination of analog and digital computing programs.

Direct input lines for controlling integrators and analog switches on one side, as well as the output signals of comparators of the analog section directly usable in the digital program on the other side, form the connection points to analog computing elements. Via digital output and input lines, the connection to the computing registers of the digital computer is established.

From the DEX it is also possible to influence the program sequence of the AR (analog computer) and DR (digital computer), as well as to control the data transfer between AR and DR and from AR to external devices.

For synchronization of analog and digital programs, the clock outputs and status feedbacks of the AR program control, the output of the clock in the interface, and fixed clocks are available.

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2. List of Abbreviations Used

Abbreviation	Meaning
AR	Analog computer (Analogrechner)
APF	Analog programming field (Analogprogrammierfeld)
DBG	Digital operating unit (Digital-Bediengerät)
DEX	Digital extension (Digitalzusatz)
DPF	Digital programming field (Digitalprogrammierfeld)
DR	Digital computer (Digitalrechner)
DVM	Digital voltmeter (Digitalvoltmeter)

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[page 5: figure only — block diagram of the DEX in the hybrid system]

Caption: Figure for Chapter 1 — Function of the DEX in the hybrid system.

The block diagram shows the interconnection of the INTERFACE with the DEX and DBG (Digital Operating Unit), and from there to the analog computing elements. Key blocks depicted include:

• INTERFACE (left): carries control lines, status lines, steering signals, integrator steering, and impulse reset; also provides interrupt and DA-converter/DA-voltmeter handoff.
• DEX (center): contains the following functional groups:
  • Zeitgeber/Betriebsartenstuerung (6.3) — Timer / Operating-mode control
  • Integrator-Steuerung (6.2) — Integrator control
  • Frei programmierbare Logik (freely programmable logic)
  • Komparator-Schalter (6.5) — Comparator switch
  • Spezial-Zählung/Steuerung (6.53/6.5A) — Special counting/control
  • Integrator-Steuer-Ausgänge (6.2) — Integrator control outputs
  • Control Lines (6.5)
  • Sense Lines (6.75)
  • Übergabe/Integriersteuerung/DA-Wandler (6.70) — Handoff / Integrator control / DA converter
  • Impulse reset (6.7S)
  • Zeitmarken-Schreiber Impulsverteilg. (6.6S) — Time-mark writer, pulse distribution
  • Kompa-Verstärker (6.1/6.2) — Comparator amplifiers
  • Anwahl-Betriebsarten, Zustands-Rückmeldung — Mode selection, status feedback
  • Anwahl-Betriebsarten, Rch.-programme (6.2) — Mode selection, computation programs
  • Betriebsarten-Steuerung (6.3) — Operating-mode control
  • Ausgang Uhr, Impulsverteig. (6.6S) — Clock output, pulse distribution
  • Integrier-Steuerig. (6.2) — Integrator control
• DBG (lower center): Betriebsarten-Steuerung, Anwahl, Betriebsarten, Rch.-programme — operating-mode control, mode selection, computation programs; Antwort-Rückmeldung — response feedback.
• External outputs (right): XY-Schreiber (XY plotter), 6-Kanal-Schreiber (6-channel recorder), DVM, Extern. Allgemein (External general), Federab-set., Zeitmarken-Schreiber, Messung/Meßbefahl, Antwort-Rückmeldung, Querverbindung/Analogausgabe.
• AD-Kanal and DA-Kanal buses are indicated at the bottom.

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3. Technical Overview

3.1 Mechanical Construction

The digital extension consists of a double-slide-in unit in one housing. Via the console-type receptacle, one of the interchangeable digital programming fields is accessible from the front of the computer (Magazine 1) — a magazine accommodating up to 24 plug-in positions for digital elements (Illustration 1).

Magazine 1 can be closed off with a Plexiglas cover. On every magazine position all offered plug-in unit types are usable interchangeably. The 24 card positions correspond with 24 addressing fields on the digital programming field, with one easily recognizable marking on the front face of the plug-in unit indicating what significance its inputs and outputs have in the particular case.

The double slide-in unit contains:

• 1 Magazine 1 with 24 plug-in positions for plug-in units with digital elements and the following plug-in units:
  • 1 Plug-in unit H-ZM 1: display of the step-switch position
  • 1 Plug-in unit H-KL 1: display of the outputs of the comparator amplifiers

For the 24 freely available plug-in positions for plug-in units with digital elements, the following plug-in units are available:

Type	Designation	Usage
H-NA 2	NAND 2	8 NAND gates with 2 inputs each
H-NA 4	NAND 4	4 NAND gates with 4 inputs each
H-NR 2	NOR 2	8 NOR gates with 2 inputs each

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(Page 7 — continuation of technical data table)

Type	Designation	Usage
H-NR 4	NOR 4	4 NOR gates with 4 inputs each
H-IV	INV	16 inverters with one input and one output each
H-GS	—	4 flipflops with 2 inputs each
H-ZL	Z	4-bit counter with 1-of-16 decoding output

Allocation plan for Magazine 1 (Belegungsplan für Magazin 1):

Slots 00 through 23 are available for the various digital element plug-in units. Slots 00–23 are shown with their addressing from 00, 01, 02, 03, 04, 05 … 20, 21, 22, 23, spanning across the address fields DK (rows).

(Diagram showing the slot allocation grid for Magazine 1 is present on this page.)

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3.2 Technical Data

Logic Potentials:

Parameter	Value
Binary Zero (log. 0)	0 V, Tolerance +1 V
For external inputs (log. 1)	0 V … +1 V
Binary One (log. 1)	+3 V … +12 V

Clock periods (Taktperiode): 1/2-T spacing

Fixed clocks (Feste Takte): 10 µs, 100 µs, 1 ms, 10 ms, 100 ms, 300 ms, 1 s, 2 s

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[page 8: figure only — illustration of the Digital Extension DEX 802 housing with the magazine open, showing the plug-in card positions]

Caption: Fig. 3.1 Digital Extension DEX 802

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4. Operating Instructions

4.1 Notes on Handling the Digital Elements

1. The plug-in units for Magazine 1 (DPF — Digital Programming Field) are removed from the housing for programming purposes.
2. Single elements of the lower row of the plug-in unit can be removed from the plug-in unit by hand and reinserted following the patching step-by-step.
3. After removing the lower element, insert the next element from the magazine into the lower position until it engages.
4. After finishing the patching, reinsert the Plexiglas cover.

4.2 Description of the Digital Programming Field (DPF)

On the left side of the DPF, the addresses are noted from 0 (FW — Digitalelemente) to 23 (last address). The Steckeinheiten (plug-in units) address indicates at its right (DK — number) which block it belongs to.

4.3 Controls and Operating Elements

a. Rotary switch and step switch (Drehschalter)

The rotary switch on the front face of the module is actuated from the DPF operating element side. It has a drive-selector function with various tabs/notches. In the operating position, when the mark on the switch is horizontal, a connection on the DPF is established between the respective middle and the above-it and below-it, connected-by-horizontal-mark bus. The printed marking on the selected bus identifies the upper and sets up a connection between the upper and lower middle bus. In this state the switch can be arrested in left or right rotation. The mark on the switch is then vertical.

b. Function switches (Drucktastenumschalter — push-button selector switches)

10 vertically arranged function selector switches with addressing D1 … D10, with a connection field on the DPF. In the normal position, when the mark on the key is horizontal, a connection on the DPF exists between the respective middle and the above and below it, indicated by a horizontal line bus. The printed marking on the key identifies the upper and establishes a connection between the upper and lower middle bus. In this state the key can be arrested in left- or right-rotation. The mark on the key is then vertical.

(A diagram of the Drucktastenschalter with labels 1–10, and Drehschalter marked “+12V” and “SYM” is shown.)

c. Operating-mode keys (Betriebsartentasten)

The two keys Run and Stop act on the yellow bus row (21/1–52). Key Run places a selected text (21/1–52) on the DPF bus row. Key Stop interrupts it. With key Stop depressed, the bus row can be freely interconnected as a multipoint bus, e.g. for input of external clocks.

Key LO resets the flipflops of the plug-in units of type FF in Magazine 1 of the digital extension. The shift registers and counters are not reset by this.

Key HT is intended for manual operation (Handtakt). If the rotary switch is also on HT, every actuation applies one clock pulse to the bus row Takt.

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5. Alphabetical Listing of the Buses of the DEX

(Pages 11–13 — alphabetical index of bus designations with section references)

Bus	Section Reference
A	6.3.1
B	6.3.4
C	6.3.4
D	6.3.4
D1 … D10	6.6.1
D1 … D10	6.1.3.2
D71	6.1.4
D81, D82	6.1.4
LR	6.5
FA1, FA2	6.1.4
FF1, FF2	6.1.4
FS	6.1.4
Grundtakt 1	6.1.3.2
Grundtakt 2	6.1.3.2
Sum (m=0 … 9, n=0 … 2)	6.5.2
Sum (m=0 … 9, n=0 … 2)	6.5.2
Sum (m=0 … 3, m=0 … 2)	6.5.2
h1	6.2.3
h2	6.2.3
hS	6.2.3
AS	6.1.3.5
S0 … I30	6.7
I0 … S3	6.4.1
IT00 … IT19	6.4.2
LZ	6.2.4
L0 … N6	6.2.4
M1	6.10
M2	6.10
M3	6.10
GR	6.7.5
GR2	6.7.5
GR3	6.7.5
GR4	6.7.5
GR1	6.7.5
CNZ	6.7.1
CS1	6.7.1
CS1	6.7.1

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(Page 12 — continuation of alphabetical bus listing)

Bus	Section Reference
CNZ	6.7.1
CNR	6.7.9
CZZN	6.2.3
P	6.2.1
p	6.2.1
p1	6.2.1
TAKT	6.7.1
TOA	6.7.1
TU	6.7.3
TV	6.7.3
U0 … U7	6.6.4
V	6.6.4
VV	6.7.4
WVS	6.5.3
Z	6.7.5
ZN	6.8.1
Zeitgeber 1 (ZG 1)	6.2.2
Zeitgeber 2 (ZG 2)	6.2.2
Zeitgeber 3 (ZG 3)	6.2.2
Zeitgeber 4 (ZG 4)	6.2.2
Zeitgeber 5 (ZG 5)	6.2.2
Zeitgeber 6 (ZG 6)	6.2.2
ZR1, ZR2, ZR3	6.2.1.5
ZRV	6.2.1.5

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(Page 13 — continuation of alphabetical bus listing)

Bus	Section Reference
1	6.1.1
1aB	6.3.7
10 N	6.7.2
1ZG	6.3.6
1 ZEG	6.3.9
2 ZEG	6.3.9
2 ZEG	6.3.9
2 µs	6.5.1.1
10 µs	6.5.1.1
1 µs	6.5.1.1
100 µs	6.2.1.1
10 ms	6.2.1.1
100 ms	6.2.1.1
2 4	6.2.7.1
0 … 15	6.9.2
1 … 13	6.7.1.2
1 … 50	6.7.2
1 … 50	6.7.2
1,4	6.7.4
10, 20, 30, 40	6.7.4
↑	6.1.3.9
–○–○–	6.1.3.9
–○–○–	6.1.3.9
⊥	—
“pulse” (accurate)	6.3.A
(plus)	6.5.A

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6. Overall Listing of the Buses and Control Panels

(Pages 14–18 — detailed tabular description of DEX buses and their control-panel pin assignments)

Section 4.1.1 — Rotary Switch (Drehschalter), Upper Contact (oberer Kontakt)

Function: Rotary switch (push-button selector switch), middle contact, upper contact.

Bus marking: —

Color: brown

Conductor number: 22–28

Layer (Lage) / Slot (Stelle): 4S–5S

Description (Wirkungsweise):

The adjacent switches (Schaltknöpfe) to the right of the rotary switch are not depressed and are connected with the respective stroke (Strich). At the depressed switch (Schaltknopf), the connection is through the upper bus and the respective lower bus/slot on the DEX plug-in contact side.

At the depressed Schaltknopf the connection is through the lower bus (“Pt…D10”) at the respective lower bus/slot on the DEX plug-in side. The bus D63 of the DEX can be found there. Bus 663 connects to the upper contact in this switching position. Switching position occurs through the respective slot; the depressed Schaltknopf is located in the horizontal position of the stroke.

(See also Fig. 7)

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Section 4.1.2 — Selector Switch, Lower Contact (unterer Kontakt)

Function: Rotary switch (push-button selector switch), middle contact, lower contact.

Bus marking: —

Color: brown (braun)

Conductor number: 23

Layer / Slot: 4S–5S (lower)

Description (Wirkungsweise):

At the depressed Schaltknopf the lower bus connection is made through the respective lower bus “Pt…D10” at the DEX connector side. The switching occurs through the respective slot; the depressed switch position results in the horizontal stroke position.

(Cross-reference: Section 4.2)

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Section 4.1.3 — Selector Switch, Free Multibus (Freie Vielfachse)

Function: Free multibus connection (Freie Vielfachse).

Bus marking: O—n—n—n— (white)

Conductor numbers: n (rows)

Layer / Slot: 3–10, 13–18, 21–26, 29–34, 37–42

Description (Wirkungsweise):

These are connected via the DPF with a single stroke line to the bus combinations, i.e. to bus combiners (Signalbuchsen, e.g. Elementsignalen) and are used for bus combinations.

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(Page 17 — continuation of bus/panel table, Wirkungsweise column only, further bus entries)

Additional bus entries (Page 17):

The Wirkungsweise column for this page is blank/empty for all listed rows — this page appears to be a continuation table where the description fields are not filled in for this segment of buses.

Layer / Slot entries recorded:

Layer-Stelle	Color	Conductor No.
15–58	weiß (white)	n
14–15	n	n
15–15	n	n
14–25	n	n
15–25	n	n
15–25	n	n
15–35	n	n
40–50	n	n
15–45	n	n
16–1	n	n
45–5	n	n
45–5	n	n
50–5	n	n
50–5	n	n

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(Page 18 — continuation of bus/panel table)

Section 4.1.4 — Interconnect Buses (Verbindungsbuchsen)

Function: Interconnect buses (Verbindungsbuchsen Rücken).

Conductor numbers / Colors:

Bus type	Conductor No.	Color	Layer
—	39–71	weiß (white)	22–22
—	—	weiß	24–22
—	—	weiß	24–22
—	—	n	31–22
—	—	n	41
—	—	n	51–22
—	—	n	61–22
—	—	n	71–22
—	—	n	81–22
—	—	n	91–22

Description (Wirkungsweise):

• For digital buses (Digitalbuchsen): connected.
• For timebase (Zeitgeber): connected.
• For digital bus (Digitalbuchsen): connected.
• For digital bus (Digitalbuchsen): connected.
• Integrated bus connection integrated at 84 MS.
• nein (no) — nein — nein — nein

Page 19

6.2 — DEX 801 → DEX 802 (continued): Fixed Clocks and Basic Clocks

Ref. No.	Meaning of the Key	Key Label / Description	Color	Zone	Row	Column	Operating Notes
6.2	Fixed Clocks	Takte	yellow	27	1–4	1–4	All clocks are derived from the central 100 kHz generator and are clocked as fixed and rectangular pulses (TPV). Between the clocks the best phase relationships are always maintained. Clocks not needed are not switched off. Clock periods from approx. 3.5 µs.
			yellow	27	1–4	1–2	TPV approx. 3/2 bit
			yellow	26	1–2	1–2	” ” ” TPV:
			yellow	26	1–2	1–2	” ” ” TPV: 4:1
			yellow	25	1–2	1–2	” ” ” TPV:
			yellow	25	1–2	1–2	” ” ” TPV:
			yellow	28	49–50	49–200	Without its own clock amplifier, in DEX 802, TPV is routed symmetrically. GT 1 and GT2: 1 ms, 100 ms, 2 s, 8T.
			yellow	29	49–50	49–200	Without its own clock amplifier, only for DEX 802. Symmetric GT only 100 ms and 2s, used for step-clocks.
6.2.1	Basic Clocks (GT)	GRUNDTAKT	yellow	25	49–52	49–52	At this location, the GT 1 (GrundTakt 1) is switched in at DEX 801, with no external clock amplifier.
6.2.1.2	Basic Clocks (GT)	GRUNDTAKT 2	yellow	26	49–52	49–52	At this location, the GT 2 (GrundTakt 2) is switched in at DEX 801, with no external clock amplifier.

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Page 20

6.2.1.3 — Clock for Stepping (Schrittsteuerung / step control)

Ref. No.	Meaning of the Key	Key Label / Description	Color	Zone	Row	Column	Operating Notes
6.2.1.3	Clock for step control (stepping clock)	ENT	yellow	28	51–58	51–58	The 500 ms clock sits at the 500-ms ground note position at DEX 801, or when the key DS with its own clock amplifier is activated (right side of the rotary switch, top on the knob). At the DEX 801 key “M” is located at the position (right side of the rotary switch, top). If the key “Stop” (known to the operator) is pressed, the clock that has been selected will be activated. “Run” and “Stop” are activated by pressing the corresponding key. It is activated automatically. Whatever other mode is selected, the clock is activated. GT 1 and GT2: 1 ms, 100 ms, 1 s, 8T. All clocks are stopped, when an SH “Q” is released, 4 b. when
6.2.1.	Clocks of the stepping selector	TAKT	yellow	21	11–58	11–58	In the DEX 801, the white key “with Halt” is pressed: a.) at DEX 801 a single-step readout of the Schrittsteuerung is possible. b.) a.) the preselected override in Übersteuerung (overload indicator) is activated. In the mode “mg” of the rotary switch, keys that have been activated are displayed. Pressed keys “mg” of the rotary switch can be given, e.g. for text display.

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Page 21

6.2.2 — Time Generators (Zeitgeber)

Ref. No.	Meaning of the Key	Key Label / Description	Color	Zone	Row	Column	Operating Notes
6.2.2	Time Generators		yellow	17	1	2–4	See Appendix 1.
	Zeitgeber 1	ZG 1 ZEITGEBER	yellow	25	2–4	7–19	Here lies during phase T₀ ‘Q’ on, otherwise ‘n’. The flags may not be used from the clocks during the phase.
	Zeitgeber 2	ZG 2 ZEITGEBER	yellow	25	11–12	7–19	Here lies during phase T₀ ‘Q’ on, otherwise ‘n’. The flags may not be used from the clocks during the phase.
	Zeitgeber 3	ZG 3 ZEITGEBER	yellow	17	19–20	20–33	Here lies during phase T₀ ‘Q’ on, otherwise ‘n’. The flags may not be used from the clocks during the phase.
	Zeitgeber 4	ZG 4 ZEITGEBER	yellow	25	34–46	34–46	Here lies during phase T₀ ‘Q’ on, otherwise ‘n’. The flags may not be used from the clocks during the phase.
	Zeitgeber 5	ZG 5 ZEITGEBER	yellow	25	27–28	27–28	Here lies during phase T₀ ‘Q’ on, otherwise ‘n’. The flags may not be used from the clocks during the phase.
	Zeitgeber 6	ZG 6 ZEITGEBER	yellow	29	7–19	7–19	Here lies during phase T₀ ‘Q’ on, otherwise ‘n’. The flags may not be used from the clocks during the phase.
	Zeitgeber 7	ZG 7 ZEITGEBER	yellow	17	30–34	30–34	Here lies during phase T₀ ‘Q’ on, otherwise ‘n’. The flags may not be used from the clocks during the phase.
	Zeitgeber 8	ZG 8 ZEITGEBER	yellow	29	34–46	34–46	Here lies during phase T₀ ‘Q’ on, otherwise ‘n’. The flags may not be used from the clocks during the phase.

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Page 22

6.2.3 — Operator Controls / Panel Controls

Ref. No.	Meaning of the Key	Key Label / Description	Color	Zone	Row	Column	Operating Notes
6.2.3	Panel Controls						See Appendix 1.
	Operator Panel (key group)		yellow	22	23–27	23	Here lies during phase T₀ ‘Q’ on, otherwise ‘n’. The flags may not be used from the clocks.
			yellow	22		23	Here lies during phase T₀ ‘Q’ on, otherwise ‘n’. The flags may not be used from the clocks.
	Operator Bit-Panel (Bit group)		yellow or similar		23–27		Here lies during phase T₀ and T₁ ‘Q’ on, otherwise ‘n’. The flags may be used from the clocks. At this location: flags 1–2.

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Page 23

6.2.3 (continued) — Complementer (Komplementierer), FF Normalization (FF-Normierung)

Ref. No.	Meaning of the Key	Key Label / Description	Color	Zone	Row	Column	Operating Notes
6.2.3	Complementer	F2	yellow	30–31	24–30	30–31	Here lies during phases T₀ and T₁ ‘Q’ on, otherwise ‘n’. The flags may be used from the clocks. It is F2 = FF. The flags may not be used during phase.
		r2	yellow	30–31	30–31	30–31	Here lies during phases T₀ ‘Q’ on, otherwise ‘n’. It is r2 = ZO9. The flags may not be used during phase.
		h2	yellow	30–31	30–31	30–31	Here lies during phases T₀ ‘Q’ on, otherwise ‘n’. It is h2 = ZO9. The flags may not be used during phase.
6.2.4	FF Normalization (Normierung)	1Bf	white	32	40–41	40–41	By connecting the two key-groups (bit shortcut — Kurzschlußstecker, i.e. clip-type short-circuit connector for the analog computer DEX 801), all flip-flops of the logic modules (connector block) are set to FF at the press of the “Pause” key, i.e. it is A = ‘Q’ and Z = ‘n’. At key 32–40 the static normalization lies in range. The normalization of the FF modules thus lies in the range 32.40. The FF operates at this instance type FF, i.e. not with ‘Q’ as a discrete component/building block.

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Page 24

6.3 — Direct Computer Control (Freie Rechnersteuerung) via DEX 802; Operating Connections

Ref. No.	Meaning of the Key	Key Label / Description	Color	Zone	Row	Column	Operating Notes
6.2.5	Override Control (Übersteuerungskontrolle)	ÜK	red	28	1–4	1–4	Here lies ‘n’ if, when: a.) at DEX 801 the central override monitoring is not activated, b.) the key “ÜK” printed on the DEX 801 is not activated. Otherwise it is always ‘n’.
6.3	DEX 802 → DEX 801: Free Computer Control via Steering Circuits
6.3.1	Free computer control via steering circuits	OP	brown (orange?)	30	16	16	Applying ‘Q’ activates the p1 control line
		OS1	”	30	17	17	Applying ‘Q’ activates the r1 control line
		OS1	”	30	18	18	Applying ‘Q’ activates the λ1 control line
		OS2	”	30	19	19	Applying ‘Q’ activates the h1 control line
		OS2	”	30	20	20	Applying ‘Q’ activates the h2 control line
							(See Appendix 1.)

At the computer control, direct routing over DEX 802 is handled as follows: when the key ‘HALT’ is pressed, this also causes all activated keys of that switch position to be suppressed — no response.

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Page 25

6.3.2 — Decade Tuning (Dekadenverstimmung) × 8 / × 8 Faster; 6.3.3 — Halt Command

Ref. No.	Meaning of the Key	Key Label / Description	Color	Zone	Row	Column	Operating Notes
6.3.2	Decade tuning × 8 faster	10 ×	white	26	28	28	Activating ‘Q’ causes: a.) both ground frequencies GT 1 and GT 2 to be raised — i.e. increased by the factor 10, accompanied also by an increase in all phase relationships as well as increase of the time-base frequencies (ZG 1…ZG 6) with reference frequencies. b.) switching off all integrator-condensers by factor 10 to a smaller value. c.) switching off the clock-generator reference voltage by factor 10 to a lower value. d.) reducing the operating voltage, i.e. the reference signal supply, by factor 10. The clock may only be used on circuit timing (GG 1…ZG 6) phases; the clock counter (ZG) also observes the flag ‘Q’ in the given GG phase. ‘n’ but. The counter may not, in the phase ‘n’ let it synchronize on its own basic clock.
6.3.3	Halt Command	H	red	26	28	28	The halt command is only used via linking components or the step sequencer, not programmatically.

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Page 26

6.3.4 — Bridge Circuit (Brücken-Schale)

Ref. No.	Meaning of the Key	Key Label / Description	Color	Zone	Row	Column	Operating Notes
6.3.4	Bridge circuit	BRÜ	yellow	26	28	28	Building elements in the ground stage of 2 output stages, T₄ has: the key ‘A₄’ as shown in the address. — When ‘Q’ is registered at DEX 801, the address registers a, T₄. — When ‘Q’ is listed at DEX 801, the address shows a, but, T₄. — In other words, when ‘Q’ is triggered — DST is set to 1, i.e. dst = 1, and dst = 1.

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Page 27

6.4.1 — Key Selector (Tastenselektor); 6.4.2 — Bit Selector (Bitselektor)

Ref. No.	Meaning of the Key	Key Label / Description	Color	Zone	Row	Column	Operating Notes
6.4.1	Key selector	SEL	various	27	28	28	The system has activated the key “Stopp” at its start position at DEX 801 and will activate the key “Stop”, “CL” at: when the start-key selector is triggered. When the DEX 801 bit selectors are activated, “Stop”, “CL” is triggered.
6.4.2	Bit Selector			27	28	28

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Page 28

6.4.3 — Time for the Bit Output (Zeitgeber at the Receiver); 6.4.4 — Time of the Flip-Flop Read-Out (Lesezeitsteuerung)

Ref. No.	Meaning of the Key	Key Label / Description	Color	Zone	Row	Column	Operating Notes
6.4.3	Time generator at the receiver (Bit-output)		yellow	28	28	28	The bit time generator at this position controls the basic bit time for normal operation of the DEX 801. The clock structure is: start — position 1, memory position 2, memory 3, etc. It covers the normal computing functions and memory management. The counter advances at each basic clock tick and steps through positions in order. During each phase, the flip-flops from all stages work in sequence. Halt commands may be issued during the Schrittphase phase. The timer goes to all halt states and can also read their states. The timer processes all half-sums.

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Page 29

6.4.3 (continued) — Time of the Flip-Flop Read-Out (continued)

Ref. No.	Meaning of the Key	Key Label	Color	Zone	Row	Column	Operating Notes
6.4.3	(continued)						With the help of D-buses it becomes possible to combine all corresponding flip-flops — in the memory position and also in the processing positions — so that at all times all states of the program can be maintained and also the program itself can be modified. The program modification steps are as follows: the process involves reading from the flip-flop groups in each clock phase, where values are compared with the program or with previous results, and logical decisions made.

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Page 30

6.4.3 (continued)

Ref. No.	Meaning	Operating Notes
6.4.3	(continued)	Furthermore, the DEX 802 can simultaneously monitor several II-buses, which gives the full selection (monitoring and processing). So the overall computing time and the precision of the overall analog processing is maintained. The operation of the basic operation via “Stopp” and corresponding key selection also enables a stepwise computation.

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Page 31

6.3.6 — Phase Change from Normal (1) to Complement (2) (Rechenphasenwechsel von Normal zu Komplement)

Ref. No.	Meaning of the Key	Key Label / Description	Color	Zone	Row	Column	Operating Notes
6.3.6	Phase change from Normal (1) to Complement (2)	VZ2	blue	27	51	51	Only when the key “Progr.” at DEX 801 is active and the programmer sets “it. sat.” or “it. land.” — the T/O transition to this phase change at the subsequent program table will take place at the earliest after the smallest ground-pause phase has ended. The T/O jump occurs at the end of the following pause phase, i.e. after at least one complete basic pause phase has passed. The timer is synchronized with the associated pause phase to the next ground clock tick. The time-error from the impulse from the Phase T₁ from the ground clock is synchronized. Phase T₁: the synchronization of the complement transition synchronizes with the program counter.
	Phase change from Normal to Complement (2) at formal level	ZZ1	blue	27	28	28	The T/O jump for the formal cycle corresponds likewise to the T/O jump from basic normal (1) to complement (2), and is always phase-synchronized to the T/O.

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Page 32

6.3.7 — G-Flag (G-Flagge) and Related

Ref. No.	Meaning of the Key	Key Label / Description	Color	Zone	Row	Column	Operating Notes
6.3.7.1	G-Flag (G-Flagge)	G + A	yellow / brown	28	28	28	In some DEX 801-states the G-flag is set: when the G-flag is active, the DEX 801 key “G” is enabled. G-flag control is via the flag line. In the state “mg”, the G + A are activated. This is also displayed on the DEX 801 display when the G flag is entered. The display status is ‘Q’ when G flag = ‘Q’.

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Page 33

6.3.7 (continued) — Display Status of the G-Flags (Anzeigesteuerung des G-Zustands)

Ref. No.	Meaning of the Key	Key Label / Description	Color	Zone	Row	Column	Operating Notes
6.3.7	Display controller (Anzeigesteuerung)		yellow	28	28	28	In place on the DEX 801 for the T₀ phase — the phase status: the display starts to act when no more basic clocks arrive, working with the programmed time zones and their normal operation. The DEX 802 switches its time units so that the display — “ZG” designation — acts accordingly. The DEX 802 is programmed to work with the display in such a way that all functions are verified and kept stable.
6.3.8	Program Storage (Programmsteuerung)		yellow	28	28	28

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Page 34

6.4 — DEX 802 for DEX 801 (General Overview Table)

Ref. No.	Meaning	Key Label	Color	Zone	Operating Notes
6.4					For driving the inputs F and F (Flipflop) of the Direktanzeige (direct indicator): the selector F3, F4, F3 and F4 from sources, as well as factors for the digital-analog connections are:
	Differential display (Differentialanzeiger)		brown	H
			brown	A
			brown	D
	Differential computer control	ZEIG	brown

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Page 35

6.4.5 — General Computing Loop Connection (Allgemeine Verbindung des Rechnereingangs)

Ref. No.	Meaning of the Key	Key Label / Description	Color	Zone	Row	Column	Operating Notes
6.4.5	Output connection to DEX 801 (Rechnereingang)	ZEIG	brown	27	27	27	This ZEIG connection: M8 to DEX (Baustein DEX 801) only. M8 to DEX (Baustein DEX 802) only.
	DEX general output connection	ZEIG	brown	27	27	27

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Page 36

6.4 — Summation of DEX 802 Basic Connections (DEX 802 Leitungsanschlüsse — summary table)

Ref. No.	Meaning	Abbreviation	Color	Zone	Row	Column	Operating Notes
6.4	DEX 802 general		white		A, B	1–3	The control inputs Y lies at: Pin M = 0 and for Pin M = 0; Pin M = 1 and for Pin M = 1. The establishment of connecting Y is: for M = 0, for M = 1. At the outputs: the pin assignments are as follows.
	Amplifier	A			a
		B			b
		C			c
		D			d
	Component connections
6.4.1	Amplifiers (Komparatoren)
					A
					B
					C
					D

Component Descriptions (continued)

Pages 37–47 — Component Table (continued)

The following pages continue the tabular listing of computing elements and their functional descriptions. Each row gives: reference designator, component type, nominal value / range, tolerance / temperature coefficient, and a “Wirkungsweise” (mode of operation / functional description) column.

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Page 37

Ref.	Component / Type	Nominal value	Tolerance	Mode of operation / Functional description
6.4.1	Inverting summer (Umkehrsummer)	—	—	Balanced summer (Gegentakt-Sommer) (see 6.4.1) / Non-inverting summer (Eintakt-Sommer) (see 6.4.1)
6.4.2	Potentiometer	—	—	—

Connections to the CPU (Anschlüsse an die CPU):

• 11 × 11 (various input/output designations)
• 13 × 13
• 14 × 14

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Page 38

Ref.	Component / Type	Nominal value	Tolerance	Mode of operation / Functional description
6.4.2	Servo amplifier / comparator connections to the CPU	1×1/2	—	Connection to the CPU at pins (Anschlüsse an die CPU): The supplementary units are connected to the CPU bus. As many as 10 supplementary units may be connected; each obtains its operating voltages from the CPU.
6.5	Input comparator / Eingangskomparator	1×1/2	—	Connections to CPU: the pins are assigned as follows (see table)
6.5.1	Left comparator / Linker Komparator — Steuereingang (control input)	—	—	—

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Page 39

Ref.	Component / Type	Nominal value	Tolerance	Mode of operation / Functional description
6.4.6	Relay contact (Relaiskontakt)	—	—	Manual description of relay contacts used for switching; each relay contact is actuated through the corresponding control line from the CPU. The relay contacts are silver-plated (versilbert) and rated for switching currents up to approx. 0.5 A. The contact resistance is less than 0.1 Ω in the closed state. Bounce time (Prellzeit) is typ. 1 ms.
6.4.7	Potentiometer set (Potentiometersatz)	—	0	Schematic arrangement (see Fig. 1): the potentiometer group consists of several individual potentiometers whose wipers are mechanically coupled.

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Page 40

Ref.	Component / Type	Nominal value	Tolerance	Mode of operation / Functional description
6.1.4	Summing amplifier / Summenverstärker	—	—	(see also Beschreibung III / Description III — Schaltung) The output voltage is: U_A = −(R_f/R_1 × U_1 + R_f/R_2 × U_2 + … + R_f/R_n × U_n). Polarity reversed. The summing point is at virtual ground. Trimming via the zero-offset trimmer (Nullpunktregler). For Abs. ZIARI (potentiometer-type reference input), the reference voltage is applied via weighting resistors. The unit is fitted with a shielded input. (Ref. also ZI-RI/potentiometer-type inputs per 6.4.1.)
6.1.4 a	Inverter / summer (Umkehr-Sommer)	—	—	Balancing / Trimming
6.1.4 b	Non-inverting summer (Eintakt-Sommer)	—	—	—
6.1.4 c	Tracking / Hold (Nachlauf / Halten)	—	—	—
6.1.4 d	Switchable gain (Schaltbare Verstärkung)	—	—	—
6.4.1	Balancing potentiometer (Abgleichpotentiometer)	—	—	Balance / Trimming

Additional row entries (continued table):

• Potentiometerblock
• Function generator (Funktionsgenerator)
• Multiplier (Multiplizierer)

Per section Abs. ZIARI: schematic function equation:

U_A = −(R_f / R_1) × U_1

The DFF (flip-flop) input is located at the back of the unit (Rückseite des Gerätes). The reference voltage is ±10 V or ±100 V depending on configuration.

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Page 41

Ref.	Component / Type	Nominal value	Tolerance	Mode of operation / Functional description
6.6	Integrator (Integrierer)	—	≤1×10^−6 / ≤1×10^−7	The integrator works as follows: the output voltage is proportional to the time integral of the sum of the weighted input voltages. In HOLD mode (Haltebetrieb) the amplifier holds (stores) the last computed value. In IC mode (Anfangswertbetrieb / initial-condition mode), the initial value stored on the hold capacitor is applied to the output. The integrator operates with high-precision capacitors. The integrating time constant is adjustable.
6.6	Integrator — type 1×10^−4	FOCO / FOCO	—	Connections are as per the standard integrator. The unit employs a “reset” scheme via (Rücksetzung).

The operating modes of the integrators are assigned to the Operate / Hold / IC modes of the computer. In OPERATE mode the integration proceeds freely. In HOLD mode the output is frozen. In IC (Initial Condition) mode the output is forced to the initial value set by the IC potentiometer.

For the integrators (A.m. the button T) reset is carried out via (Rücksetzung) in double-precision mode. The integration result can be read out directly at the output terminal.

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Page 42

Ref.	Component / Type	Nominal value	Tolerance	Mode of operation / Functional description
6.6.2	Integrator, type …	No. …PP	—	Changing the mode of operation: In OPERATE mode, the output voltage changes in accordance with the integral. Switching to HOLD mode via (Betriebsartenumschaltung): the program running on the CPU controls the mode-of-operation signal (Betriebsartensignal). The mode is transmitted as a logic level and sets the integrators simultaneously. The transition from OPERATE to HOLD is accomplished in approx. (transition time). The units are arranged in groups of 4; group addressing is possible.

The mode is: X = No (none). The associated logic level is blau (blue).

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Page 43

Ref.	Component / Type	Nominal value	Tolerance	Mode of operation / Functional description
6.7.1	Comparator, left / Linker Komparator	720	—	The signal is applied to the reference input of the comparator (Referenzeingang). A comparison is made with the input variable. At the switching point the output changes state. The output signal is connected to the Betriebsartensteuerung (mode-of-operation control). Hysteresis can be set via an internal trimmer (Hysterese einstellbar). The switching threshold is adjustable between −10 V and +10 V; the default is 0 V. At the output, a logical “1” or “0” is generated depending on whether the input exceeds or falls below the threshold. For use with the comparator function (from 7/7.1 onwards).

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Page 44

Ref.	Component / Type	Nominal value	Tolerance	Mode of operation / Functional description
6.7.7	Timer (Zeitgeber)	—	—	Binds the connected unit to an internal time base. The timer generates a precise time interval. The time range (Zeitbereich) is selectable. Internal oscillator with crystal reference for high accuracy. The output is a rectangular pulse (Rechteckimpuls) of adjustable duration. The timer can be started, stopped, and reset externally by the CPU mode-of-operation signals.
6.7.8	Input limiter / Eingangsbegrenzer	—	—	Limits the input signal to a preset voltage level, protecting downstream components from overload. Both positive and negative clamping levels are independently adjustable via potentiometers.
6.7.1	Output limiter	—	1,7	—

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Page 45

Ref.	Component / Type	Nominal value	Tolerance	Mode of operation / Functional description
6.7.4	Servo amplifier / Servoverstärker	11…100	2×(0…6+2)	Single-stage bridge comparison device (Brückenvergleichsgerät). The servo amplifier output is connected to the servo motor and drives it in the direction that reduces the error signal to zero. The servo motor shaft position corresponds to the programmed value. The reference (Führungsgröße) is supplied by the CPU. Accuracy of position: typ. ±0.05 % of full scale. Resolution: better than 0.01 % of full scale.
6.7.7	Address decoder (Adressdekoder)	—	—	—

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Page 46

Ref.	Component / Type	Nominal value	Tolerance	Mode of operation / Functional description
6.4.8	Element group / Elementgruppe — see also CPU	279	—	For each x N m, the element group (Elementgruppe) sets the value on the patch panel. The reference value is generated internally. For the timer channel (Zeitkanal): at each N m step a time base pulse is generated. Connections to the CPU output. The Steuerspannung (control voltage) on the CPU.
6.4.9	Multiplier (Multiplizierer)	—	—	Variable output (Variationsausgang). The output signal is proportional to the product of two input variables. Maximum input voltage: ±10 V. Maximum output voltage: ±10 V.
6.4.7	Divider (Dividierer)	—	—	Division of one signal by another.

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Page 47

Ref.	Component / Type	Nominal value	Tolerance	Mode of operation / Functional description
6.4.8	Voltage-controlled oscillator (spannungsgesteuerter Oszillator)	—	—	The Tr-Anschluss (trigger connection) controls the oscillator. The oscillator frequency is proportional to the control voltage. Output is a rectangular waveform. Connections: T = “Trigger”, “Basis” (base), “Eingang” (input), “Ausgang” (output). The oscillator output is fed to the patch panel and can be connected to any computing element.
6.4.5	P-T¹ element (lag element)	—	—	A first-order lag element (Verzögerungsglied erster Ordnung). Transfer function: G(s) = 1 / (1 + T·s). The time constant T is set via the potentiometer on the front panel. The element consists of a computing amplifier with a resistance-capacitance feedback network. The output is the smoothed (filtered) version of the input signal.

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Pages 48–53 — Schematics / Diagrams

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Page 48 — [Figure: Schematic — computing element patch panel wiring, type 1]

This page shows the circuit diagram for a computing amplifier computing element connected to the standard patch panel (Steckfeld). The diagram illustrates:

• Input network: The computing element receives its input signals via the patch panel row. Input resistors are weighted (R₁, R₂, … Rₙ) to implement the desired gain coefficients.
• Feedback network: A feedback resistor R_f (or capacitor C for integration) connects the amplifier output back to the summing junction (Summierpunkt).
• Symbol key (Legende):
  • Symbol for the operational amplifier (Operationsverstärker) with non-inverting (+) and inverting (−) inputs.
  • Symbol indicating the initial-condition (IC) network (Anfangswertglied): a capacitor pre-charged to the initial value.
• Patch panel row: a row of jacks corresponding to the inputs, outputs, and mode-of-operation signals for this computing element.
• Output (Ausgang): labelled “Ausgang Uy = ·s”.
• Parameters table (Parametertabelle): upper right corner — a small table listing the configurable parameters for the element (e.g., time constant range, gain range).

Section heading (lower left):
7. Beschreibung der maschineninternen Baugruppen (forts.) — Description of the machine-internal assemblies (continued).
7.1 Kassette (CBS) — Cassette (CBS).

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Page 49 — [Figure: Schematic — computing element, type 2]

This page shows the circuit diagram for a second computing element variant, including:

• Summing amplifier circuit with multiple weighted input resistors and a feedback resistor. The output voltage is given by the relation:
  U_A = −(V₁·U_E1 + V₂·U_E2 + … + Vₙ·U_Eₙ)
  where V_i are the weighting factors set by the resistance ratios.
• Symbol: the standard operational amplifier triangle symbol with summing junction at the inverting input.
• Initial-condition (IC) input with the switch (Schalter) for IC/HOLD/OPERATE mode selection shown symbolically.
• Parameters table: upper right — lists time constant, capacitor value, and gain range.
• Patch panel connections: lower part of the figure shows the patch panel jack assignments for this element.

Section heading (lower left):
7.1 Kassette CBS — Kennliniengeber (forts.) — Cassette CBS — Function generator (continued).

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Page 50 — [Figure: Schematic — computing element, type 3 (integrator)]

This page presents the integrator element schematic:

• Integrator circuit: The feedback element is a precision capacitor C rather than a resistor. Output is:
  U_A = −(1/C) × ∫ (U_E1/R₁ + U_E2/R₂ + … + U_En/Rₙ) dt + U_A(t₀)
  where U_A(t₀) is the initial condition voltage.
• IC network: The initial-condition (Anfangswert) voltage is applied via a separate switch path; in IC mode the capacitor is pre-charged to U_A(t₀).
• Mode switching: The symbolic switches for IC / HOLD / OPERATE are shown in the schematic.
• Parameters table: upper right — lists the available capacitor values (time constant selection) and input resistance values.
• Patch panel connections: lower section.

Section heading (lower left):
7.1 Kassette CBS — Kennliniengeber (forts.) — Cassette CBS — Function generator (continued).

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Page 51 — [Figure: Schematic — computing element, type 4]

This page shows a further computing element variant:

• Circuit: Features a four-input operational amplifier configuration. Output relation:
  y = −(x₁·D₁ + x₂·D₂)
  where D₁, D₂ are the respective weighting coefficients set by the resistor network on the patch panel.
• Symbol: Standard opamp triangle with multiple inputs at the inverting summing junction; non-inverting input tied to reference.
• Parameters table: upper right — two-row, two-column table listing parameter ranges (e.g., gain factors 1 and 10).
• Patch panel row: lower portion.

Section heading (lower left):
7.1 CBS — Kennliniengeber (forts.) — CBS — Function generator (continued).

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Page 52 — [Figure: Schematic — computing element, type 5 (multiplier / divider)]

This page presents the multiplier/divider element:

• Circuit topology: A quarter-square multiplier or a servo-type multiplier. The output is:
  y = −(x₁·D₁ + x₂·D₂ + x₃·D₃ + x₄·D₄)
  (four-quadrant or one-quadrant, depending on configuration).
• Feedback and summing network involving multiple resistors and the multiplier core.
• Symbol: The multiplier symbol with the product sign (×) enclosed in a circle.
• Patch panel connections: lower section shows the jack assignments for X1, X2, Y inputs and Z output.
• Parameters table: upper right — lists scaling factors and input/output voltage ranges (±10 V).

Section heading (lower left):
7.1 CBS — Kennliniengeber (forts.) — CBS — Function generator (continued).

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Page 53 — [Figure: Schematic — complete CBS cassette internal circuit]

This page shows the full internal circuit of the CBS (Cassette / module) type:

• Symbol legend (Symbol / Legende): upper right corner lists all symbols used in the schematic:

  • a = Switch (Schalter)
  • b = CT-type transistor switch (CT-Transistorschalter)
  • c = Diode clamp (Diodenbegrenzer)
  • d = Zener diode (Z-Diode)
  • e = Computing amplifier (Rechenoperationsverstärker)
  • f = Relay (Relais)
  • g = A₁ / U₁ / U₂ labeled nodes

• Hauptschaltbild (main schematic): Shows the complete signal path through the CBS cassette:

  • Input from patch panel (Patchfeld) through the input resistor network to the summing junction.
  • The computing amplifier (Rechenverstärker) stage with feedback elements.
  • IC / HOLD switching via relay contacts and capacitors.
  • Output stage back to the patch panel output jack row.
  • Mode-of-operation signals (Betriebsartensignale) entering the switching logic from the CPU bus.

• Klemmenleiste (terminal strip): Lower section — detailed table of all connector pin assignments for the cassette, numbered PP (Patch Panel rows) with signal names and directions (input / output / bidirectional).

Section heading (lower left):
7.4 Kassette CBS — Cassette CBS.

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Page 54 — Section 7.6: Flip-Flop (Flipflop)

7.6 Flip-Flop (Flipflop)

The flip-flop circuit contains one flip-flop and associated gating (Torschaltung) for each comparator output. The description of the inputs is as follows (see also Section 7.5–13):

• S = Set (statically pre-settable / statisch voreinstellbar)
• R = Reset (statically resettable / statisch rückstellbar)
• T = Trigger (clock input / Takteingang)
• T = Complementary trigger / Negierter Takt (dynamically settable / dynamisch einstellbar)

In the normal operating mode, the output of the flip-flop drives input A of the next flip-flop. If input S and input R are both at 0, then both outputs of the flip-flop are equal, and there is no valid flip-flop state (ambiguous condition).

If S = 0 and R = 0, both outputs of the flip-flop light up (Binäranzeige / binary indicator lamps, Bild 1).
If S = 1 and R = 0, output A goes to 1 and output B goes to 0.
If S = 0 and R = 1, output A goes to 0 and output B goes to 1.

If S = 1 and R = 1, a changeover flip-flop (Wechselflipflop) is formed, i.e., the output changes with each successive clock pulse (T-flip-flop behavior).

If S = 0 and R = 0 with T = 1 and T̄ = 0, the state is held. In the other case of T = 0 and T̄ = 1 (Binärtakt), the state is clocked through.

For S = 1 and R = 1, the flip-flop forms a counting / toggle flip-flop (Zählflipflop); on each rising edge of the clock input, the state toggles. Together with the associated gate circuitry, this allows the flip-flop to be configured as an input for the mode-of-operation control (Betriebsartensteuerung) of the analog computer.

The triggering of additional flip-flops (from the A output to the next flip-flop T input) is possible, thereby building a flip-flop chain (Flipflopkette).

The comparison of analog signals (from input A and input B) is evaluated by the comparator and fed into the flip-flop; the result is available at both the true (Q) and complementary (Q̄) outputs.

The digital output of the flip-flop stages (Kap. 7.6) is used for the Betriebsartensteuerung (mode-of-operation control) of the analog computer units.

7.7 Shift Register (QB)

[page 55: figure only — schematic diagram, card layout diagram, and symbol for the shift register plug-in unit (QB). The schematic shows four cascaded flip-flop stages with serial-entry and serial-reset inputs S_s / R_s, a clock input T, a load input E, a clear input L, and parallel outputs A_1 through A_4 at card-edge positions 0–3, 4–7, 8–11, and 12–15. The symbol block is labelled with pin designations. A footnote states: “The interconnections between the outputs Q, Q̄, C_1, C_2 … of one stage and the inputs of the next stage are internal and are indicated at the outputs of the group. A_1, A_2 etc. are the outputs of the group A_1, A_2 …”]

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Notes on Section 7.7 (Shift Register)

The plug-in unit contains a four-stage shift register consisting of four flip-flops. The outputs of the flip-flops are located at card-edge positions 0–3, 4–7, 8–11, and 12–15. Each flip-flop has two parallel outputs: the normal output and the inverted (negated) output signal. The indicator lamps for each flip-flop illuminate when a logical 1 appears at output A.

Description of Inputs

• S_s, R_s — Serial-set and serial-reset inputs. These allow a new item of information to be entered into the first stage. In the event of simultaneous application of a clock pulse on T and a signal changing from 0 to 1 on S_s, S_s and R_s are each active as long as a logical 1 is applied to inputs L (clear) and E (store). A logical 1 must be present at both these inputs.

• S — Shift. Input S must be held at logical 0 and simultaneously a clock pulse must be applied to T so that the information can be shifted into the following stages and S_s and R_s made active. Simultaneously, logical 1 must be present at inputs E (store) and L (clear).

• E — Store. This input enables the presetting of individual flip-flops of the shift register. For this purpose E must be held at logical 1 and a clock pulse applied to T. The desired starting value is entered in binary form by holding the corresponding flip-flop inputs S_1 and R_1 statically at 0. Alternatively, with E held at logical 1, the inputs S_s, R_s through S_4, R_4 together with a single clock pulse on T can be used to load all stages simultaneously.

• L — Clear of all flip-flops in the shift register. Clearing occurs upon the arrival of a clock pulse on T when L is held at logical 0.

• T — Clock input. Required for all changes to the shift register.

Unconnected inputs act as if tied to logical 1.

For output loading capacity, see Section 8.

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7.8 Counter (Z)

[page 57: figure only — schematic diagram, card layout diagram, and symbol for the counter plug-in unit (Z). The principal schematic shows four flip-flop stages with decode logic for counts 1 through 16. The symbol lists inputs Z_s (static count input), Z_D (dynamic count input), S_1–S_4 (preset inputs), R_1–R_4 (preset reset inputs), E (store), L (clear), T (clock), and outputs D_0 through D_8 with associated indicator lamps. A note states: “At the static output Z the signal Q is taken from output D_0 Q1.” A second note: “The static counter inputs on all interconnection members and generally also the preset inputs of the counter must not be switched to the dynamic clock input.”]

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Notes on Section 7.8 (Counter)

The plug-in unit Z contains a counter consisting of four flip-flops with decoding for counts 1 to 16. In every count state the associated output provides a logical 1 along with simultaneous illumination of the corresponding indicator lamp.

Description of Inputs

• S_1, R_1 … S_4, R_4 — Inputs of four flip-flops for use when presetting the counter. Entry of the desired starting count is accomplished in binary form by holding the corresponding flip-flop inputs S_i and R_i statically at logical 0. If input E is simultaneously held at logical 0 and a clock pulse appears at T, the counter is set to the value presented.

• E — Store. Control input for presetting the counter. For this purpose E must be held at logical 0 and a clock pulse must arrive at T.

• L — Clear. Clearing occurs upon the arrival of a clock pulse at T when L is held at logical 0.

• T — Clock input. Required for both storing and clearing the counter.

• Z_s — Static count input. Counting of the counter over input Z_s may only take place as long as the dynamic count input Z_D is at logical 0.

• Z_D — Dynamic count input. The counter increments on the dynamic clock signal.

The counter outputs must not be switched to the dynamic clock input. Through appropriate wiring the counter can be programmed as a ring counter for any desired modulus. For output loading capacity, see Section 8.

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Notes on Section 7.8 (Counter) — continued

[page 59: figure only — table showing the presetting states of the counter. The table is headed “Voreinstellung des Zählers” (Presetting of the Counter) and lists all sixteen combinations of flip-flop states S_1 through S_4 (expressed as binary values 0 and 1) for counts 0 through 13, with columns for S_1, S_2, S_3, S_4, R_1, R_2, R_3, R_4. The table represents the binary encoding required to preset the counter to each specific starting value.]

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7.9 Monoflop (MF)

[page 60: figure only — front-panel layout of the Monoflop plug-in unit, showing card-edge pin assignments. The layout identifies inputs S (Set), T (Trigger/Clock), and time-constant control inputs including a potentiometer, and outputs A and Ā. Pin assignments are shown for positions along both sides of the card edge.]

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Notes on Section 7.9 (Monoflop)

1. Purpose and Type of the Plug-in Unit

The monoflop plug-in unit II-MF 1 55.3005.707-00 completes the program of digital elements in the DEX 802 digital add-on set and can be inserted at will into card positions 00…23 of Magazine I. The plug-in unit contains four mutually independent monoflops, each of which is capable of generating output pulses with a pulse width from 10 µs to 1.22 s.

2. Input and Output Designations; Function of the Plug-in Unit

The designations and arrangement of the inputs and outputs are located on the plug-in unit back-panel bus (Fig. 1). The middle numeric sequence on the bus is identical with the byte address on the digital programmer field and facilitates the location of individual bytes. The byte affiliation to a monoflop is spatially delimited by the indicator lamp opening and, in addition to the time-range byte, is identified by indexing.

Activation of the monoflop is accomplished through inputs S and T. A logical “0” must be applied to the preset input S; the trigger should be applied as a 1/0 → 0 transition (falling edge) on T. In the quiescent state output A is at logical “0” and the associated indicator lamp is extinguished. As soon as the monoflop is activated and a logical “1” appears at A, the lamp lights. The pulse width of the monoflop output is determined by the time-influencing inputs G: 0.1; 1; 10; 100, which are fixed in value. The digits are dimension-dependent. Depending on the desired pulse width, the corresponding input must be held at logical “0.” In addition to this stepped switching, a continuous fine adjustment of the time can be made using the potentiometer. The time value of the byte setting must be multiplied by the potentiometer scale value to obtain the set pulse width of the output pulse.

A speed increase by a factor of 10 is obtained by holding byte F at logical “0,” i.e., all time values must be divided by 10.

Beside F, the byte ZSA (time-constant control output) is provided. It is identical with byte ZSA on the digital programmer field and supplies a logical “0” to the digital programmer field. When the computer runs at 10× speed, i.e., byte F on the digital programmer field is held at logical “0” — which causes F and ZSA to be connected via a short-circuit plug — the monoflop is included in this process.

Timing Diagram

Fig. 21: Timing Diagrams

The figure shows timing diagrams for the monoflop output pulse at various G-settings. The horizontal axis is the output pulse length T_L in milliseconds (range shown: 0.01 to 1000 ms). Hatched zones correspond to settings G = 100, 10, 1, 0.1 ms, each covering approximately one decade. The formula for the output pulse length is:

T_L = G · P / F

where: G = 0.1; 1; 10; 100 (time range in ms), P = 1 to 12 (potentiometer setting), F = 1; 10 (speed factor).

In the unconnected state all inputs act as if tied to logical “1.”

[page 63: figure only — circuit diagram of the monoflop, showing the internal schematic with –12 V supply, the RC timing network connected to the potentiometer (values marked 0.1, 1, 10, 100, F, ZSA), and the output buffer stage labelled “10 × schneller” (10× faster). The schematic also shows the indicator lamp driver circuit and the output inverters for A and Ā.]

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8. Loading Capacity of Operating and Control Elements of the DEX 802

8.1 Operating Elements

At outputs (in standard loads):

Name of Element	Normal Verknüpfungsglied (logic) output	Takteingangs-output (clock output)
EXY	12	30
NUD 0	12	—
NUD 1	12	—
NOR 2	12	—
KOR E	1 × xxx	—
FF as J-K-FF	10	12
FF as D-FF	10	12
AP	12	—

Notes:

• Each J-K flip-flop includes one flip-flop in J/K and one J-K flip-flop in PR and FF as well as one J-K flip-flop counted in at the clock inputs (Takteingang) [Fehlanzeige/not applicable].
• ** Diagrammed inputs cannot be connected to the counter. The interconnection output (Verschaltungsausgang) must not exceed the takt-input loading over Z_D.*
• *** For programming of NOR connections with more than 4 inputs, the number of usable Verknüpfungsglied outputs and preset/serial inputs is as follows:

Number of usable preset/serial inputs	Corresponding Verknüpfungsglied outputs
1	4
2	3
3	2
4	1

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8.2 Oscillators and Clock Circuits

At outputs (in standard loads):

Designation	Normal Verknüpfungsglied output	Takt output
HF	30	30
1 s	30	30
100 ms	30	30
10 ms	30	30
1 ms	30	30
100 µs	7	7
GENERATOR T	14	14
GENERATOR T̄	14	14
ZEITKREIS T (see [ref. 14])	14	14

8.3 Interconnections and Other Elements

	Total quantity
FF, AP, NOR,QB,Z,MF (across Verknüpfungsglied, Preset, 12)	—
all AND, NAND, NOR, XNOR, XAND (Verknüpfungsglieder, Versp., 1)	2
AP	7
prob. SPL, bahn abs	10
SPL	10
G. abs	13
G. abs et	13

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9. Input Levels of Operating and Control Elements of the DEX 802

Input level (in standard loads):

Type of Element	Input designation	Verknüpfungsglied and preset/serial inputs of Typ FF	Takteingang (clock input)
FF	S, C	2 V	—
	T	—	2 V
	R, S	—	—
Z	Z_s	2 V	—
	Z_D	—	2 V
Rong-Schalter (Ring-switches)	A	2 V	—
(ISA-Schalter)	B	2 V	—
Steuerleitungen (Control lines)	HE	8 V	—
	SE	8 V	—
	IZ2	8 V	—
	IZ3	8 V	—
	N	12 V — only at Verknüpfungsglied and preset inputs	—

Non-activated inputs present the logical level 1 dar. A logical 0 is that level which is less than or equal to approximately 0.4 V above the lower reference level.

The inputs K, L, and S are interchangeable as they operate simultaneously as clock inputs.

The activation level of the preset inputs FF, QB, and Z is defined by the Voreinscheider (pre-selector) and amounts to approximately 2 V (0.7 V + 1.3 V). The activation of the clock output (Taktausgang) by Typ T amounts to approximately 2 V.

Fanout Capability:

The maximum drive capability (Aussteuerungsgrenze) of the DEX 802 logic follows the logic defined in:

Logical 0: U_0 = 0 V (2·(+0.4) V) Logical 1: U_1 = 12 V (–1.5 V … +1.5 V)

The maximum Aussteuerung (output swing) of the DEX 802 bus amounts to ±12 V.

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Appendix 1: Timing Diagrams for the Control Lines

[page 67: figure only — detailed timing diagram for control-line signals. Two sections are shown:

DEX 802 — Eingabe (Input): Shows timing relationships for the signals:

• Taktsignal (clock signal)
• AP (output latch)
• A_1–A_4 (address lines 1–4)

Relative timing marks indicate setup and hold times referenced to the rising and falling clock edges. Multiple clock cycles are depicted with the address lines changing state shortly before a clock edge.

DEX 802 — Ausgabe (Output): Shows timing relationships for:

• Taktsignal (clock signal)
• FF-1 … FF-4 (flip-flop states 1–4 as bus output lines)
• A1–A4, +A1–+A4 (address and inverted-address outputs)
• Z/D (count/data lines)
• ZD4 → A1 (counter decode to address 1)
• ZD4 (counter decode output)
• ZD4 + A1 (combined)

The diagram shows that outputs update on specific clock edges relative to the address bus transitions, with annotations indicating minimum and maximum propagation delays. The lower portion of the figure contains an explanatory note (partially legible) indicating that the timing applies to the standard operating frequency, and that timing margins may be reduced at higher clock rates.]