Dead-Time Elements for the Dornier DO 80 Analog Computer — Procurement and Development File

This document translates and summarizes a German-language compilation of correspondence, technical descriptions, circuit diagrams, and supplementary material relating to the development and procurement of dead-time delay elements (Totzeitglieder) for the Dornier DO 80 analog computer, circa 1973–1975.

1. Letter from Dornier-System GmbH — Request for Quotation (22 August 1974)

From: Dornier-System GmbH, 7990 Friedrichshafen, Postfach 648
To: Dr.-Ing. Wilhelm Becker, 4770 Soest-Westf., Jakobi-Nütten-Holl 18
Reference: VCE MA/PL
Author: Dipl.-Ing. Marklein, Tel. (07545) 8–2730

Subject: Quotation for Five Dead-Time Elements

The letter requests a quotation for the manufacture and testing of five dead-time elements (Totzeitglieder) for the DO 80 analog computer, on the following terms:

Dornier lends the layout of the Totzeitglied circuit board free of charge so that any necessary corrections can be made. After correction, the layout is returned to Dornier.
Dornier also makes available, on loan and free of charge, a [reference unit] for comparison purposes.
Dornier supplies the required circuit boards and patch blocks for manufacture at no charge.
The contractor provides a warranty (under Dornier conditions: 12 months after acceptance, at most 13 months after delivery) for the functional performance of the dead-time elements.

A quotation is requested by the end of September 1974.

Signed: Dr. Beller / Marklein (i.A.)

2. Siemens Letter and Preliminary Product Notification (2 September 1974)

From: Siemens AG, Zweigniederlassung Dortmund, Vertrieb öffentlicher Auftraggeber
To: Gesamthochschule Paderborn, Abt. Soest
Author: Rickert/Pu

Subject: Quotation — Analog Computer

Siemens informs the DO 80 user community that a dead-time element (Totzeitglied) for this computer is in preparation. Further technical details are provided in the enclosed preliminary description (see Section 3 below).

The Totzeitglied will be available from January 1975 at a list price of DM 3,500 (net, plus VAT).

A demonstration is possible at the DORNIER trade-fair stand, Hall 5, Stand 5017, during HANOVER MESSE (INTERKAMA).

3. Preliminary Technical Description — Dead-Time Elements for the DO 80 Analog Computer

3.1 Introduction

For the simulation of technical processes it is frequently necessary to model a dead time (Totzeit), i.e., a system with the transfer function:

F(p) = e^(−pT)

The approximation of this transfer function using linear methods (Allpass, Padé approximation) is generally exact only at a single frequency.

For this reason it was decided to extend the component programme of the DO 80 analog computer with a dead-time generator (Totzeitgenerator).

3.2 General Description

Figure 1 shows a schematic diagram of the dead-time generator’s construction.

The input voltage is digitized in an 8-bit analog-to-digital converter. The digital value is fed to a shift register (SR) with a length of 100 words. After passing through the shift register, the value at the output is converted back to an analog value via an 8-bit digital-to-analog converter.

The conversion and shift clock is generated by an internal clock generator operating at base frequencies of 1 kHz, 10 kHz, and 100 kHz. These frequencies can each be continuously reduced by a factor of up to 1/1000 via the input (continuously variable). This also makes it possible to model a dead time that varies during the computation.

By means of switch S, operation as a function generator is possible. When the switch is toggled, a function once stored in the shift register is re-issued cyclically in accordance with the shift clock (ring shift register).

3.3 Preliminary Technical Data

Parameter	Value
Construction	One single-width DO 80 plug-in module
Input voltage range	−10 V to +10 V
Output voltage range	−10 V to +10 V
Max. output current at 10 V	5 mA
Output short-circuit and reverse-voltage protection	Against all DO 80 internal voltages
Accuracy	8 bits (incl. sign), approx. 80 mV error
Shift register length	100 positions

Dead-time adjustment ranges via T_f input (continuously variable):

1 ms to 100 ms
10 ms to 1 s
100 ms to 10 s

4. Internal Dornier Memorandum — PCB Base Material (25 September 1973)

Reference: EE IO-M-56/73
Subject: Base material types FR-4 and G10 from Dynamit Nobel

Due to increased failures of the above-mentioned base material through delamination during soldering, EE IO carried out thorough investigations in this area using base materials from several manufacturers. The following manufacturers were qualified as suppliers of glass-fibre epoxy base material types FR-4 and G10:

UOP Bisterfeld
Maas
Ferrozell
Isola u. Stolting

The ranking in the list corresponds to their qualification order.

Suppliers for base material are not liable under their general terms and conditions for consequential damages attributable to poor material, and therefore cannot be held responsible for potential schedule delays or downtime.

In future, all requests for through-plated circuit boards should include on the order form to Purchasing a note indicating the manufacturer of the base material.

5. Internal Dornier Memoranda — Document Distribution Lists (18 February 1974)

Two internal memos (EESK-M39/74 and EESK-M40/74) establish distribution lists for mechanical and electrical documentation of analog computers. Recipients include engineering departments (EBRE, EEPC, EESK, EEF) and Dr. Becker (Do GmbH), restricted to the document number range FK 891.4XXX.

6. Internal Dornier Memorandum — Pre-Production of Logic Components (circa 1974)

Reference: VCE VCZ0-b1-2/74
To: Dr. Klink, EMA
From: Marklein, VC 2A

Subject: Pre-production of Logic Components

For the DFVLR-Oberpfaffenhofen, availability of logic components is a prerequisite for placing orders. A pre-production run is requested of:

1 clock generator plug-in module
2 flip-flop plug-in modules
3 gate plug-in modules

Latest delivery date to DFVLR: end of February 1974.

Additional units for demonstration purposes (2 clock generators, 4 flip-flops, 4 gates) are also requested as early as possible. All plug-in modules may be delivered with a blank patch block.

7. Totzeitglied Circuit Diagrams and Technical Development Material

[Sections 7 and 8 of the original file consist primarily of handwritten schematic diagrams, circuit lists, component tables, and internal engineering notes. The text layer extraction yields fragmentary data; key parameters recoverable from the text fragments include:]

Flip-flop stages: FF1, FF2, FF3 configurations
Clock circuitry using quartz-stabilized frequency references
Shift register organisation: 100 words × 8 bits
D/A and A/D converter interfacing
Pin/connector assignments for the DO 80 backplane

8. Supplementary Reference Material

8.1 Helipot Resistor Networks, Series 898/899 — Data Sheet (Bulletin M-3015A)

Manufacturer: Helipot (Beckman)

These dual-in-line (DIP) thick-film resistor networks are designed for high reliability in industrial and military applications.

Series 899-1 / 898-1: 13 or 15 resistors in 14- or 16-pin DIP packages; all resistors have equal values with a common terminal. Typical use: pull-up/pull-down networks between 10 outputs/inputs and supply voltage or ground.

Series 899-3 / 898-3: 7 or 8 thick-film resistors with equal values; individual resistor terminals are connected to individual pins. Typical uses: symmetrizing and terminating measurement leads, current limiting for digital driver circuits.

Series 899-5 / 898-5: 24 or 28 resistors in groups of 2 series-connected pairs; typical use as pulse-matching networks.

Advantages: 7:1 cost saving versus individual resistors for PCB assembly; compatible with automatic board-stuffing equipment; largely meets MIL-Std-202 and MIL-Std-883 requirements.

8.2 AEG-Telefunken Electronic Delay Unit LZG 100 — Information Sheet AIB 067

Manufacturer: AEG-Telefunken, Fachbereich Anlagen Informationstechnik, 775 Konstanz

Intended use: Extension module for the hybrid precision analog computers R4770 and RA800 HYBRID, as well as for TELEFUNKEN desktop analog computers.

Operating modes:

Delay: The input signal is delayed by time T before re-output.
Hold: Input sampling ceases; the current output value is held.
Pause: Input sampling ceases; memory is cleared; output is set to zero.
Recirculate (Umlauf): Input is not sampled; the memory content recirculates cyclically and is continuously output. May be combined with Hold mode.
Shift register: The input signal is sampled only at intervals of 10 clock steps and shifted from one intermediate output to the next at each sample.

Operating principle: The LZG 100 operates as a sampling system with digital storage. A clock-driven A/D converter produces a 10-bit signal that is fed to a 100-word dynamic memory (MOS shift register). After 100 clock cycles the 10-bit signal is fed to a D/A converter to yield an analog output. The D/A converter uses a variable reference so that the delayed signal can simultaneously be multiplied by a variable. Intermediate outputs at n × 10 clock steps (n = 1…10) allow the signal to appear with different delay times. The clock determining the delay time can be generated internally or supplied externally. The internal clock generator is electrically controllable via digital switch K and potentiometer U:

T = K · U [s], where K = 1…999, U = 0.1…1.1

U may also be entered as an external analog variable.

Technical Data:

Parameter	Value
Input voltage range	−10 V ≤ Ue ≤ +10 V
Output voltage range	−10 V ≤ Ua ≤ +10 V
Accuracy	±0.2% referred to full scale
Maximum delay time	1000 s (expandable to 10,000 s)
Delay accuracy (internal clock)	±1%
Delay accuracy (external clock)	±1%
Voltage range for electrical delay control	+1 V ≤ Us ≤ +11 V
External control signals (Halt, Pause, external clock)	0 ^ 0…+2 V; 1 ^ +8…+15 V
Power supply	220 V −15%…+10%; 50 Hz; 60 VA

Construction: A complete 19-inch plug-in module in a housing. All components are on plug-in printed circuit cards connected via a backplane PCB. All controls, inputs, and outputs are on the front panel.

8.3 Article: Monte Carlo Sampling Technique (from Electronic Design, 1 February 1973)

[Condensed — this English-language article on the Monte Carlo simulation method was included as supplementary reading material. It explains the technique for solving probabilistic management and engineering problems using random-number sampling against cumulative probability distributions. Example applications include inventory optimization and queuing/waiting-line problems in hybrid circuit manufacturing. The article notes that Monte Carlo is “the only logical approach” where conventional analytic solutions are impractical. The article is in English and requires no translation.]

End of translation.