EAI MiniAC Reference Handbook
MiINIAC
ANALOG/HYBRID COMPUTING SYSTEM
REFERENCE HANDBOOK
CONTENTS
PART | — FAMILIARIZATION AND GENERAL OPERATION (FOR ALL USERS)
CHAPTER 1 — INTRODUCTION
1.1 THEEAIMiniAC 2. 1. .
1.2 PURPOSE OF MANUAL . ww ww we ee
1.3 STRUCTURE OF MANUAL ... 1 1 1 we
1.4 HOW TO USE THIS MANUAL .. 1 6 we ee es
CHAPTER 2 — MACHINE ORGANIZATION
2.1 INTRODUCTION
2.2 THE ANALOG COMPONENTS
2.4 . THE ANALOG/LOGIC INTERFACE COMPONENTS
2.5 THE CONTROL AND MONITORING SYSTEMS
2.6 THE PATCH PANEL
2.6.1 Introduction
2.6.2. Patch Panel Layout
2.7 DVM AND COEFFICIENT POT PANEL
2.8 VFG PANEL
2.9 THE ANALOG CONTROL PANEL
2.10 THE LOGIC CONTROL PANEL
2.11. SETUP SWITCH/OVERLOAD INDICATOR PANEL
2.11.1 Introduction
2.11.2 The Identification Strip... ........,
2.11.3 The Setup Switches
2.11.4 Amplifier Balance Controls
2.11.5 The Overload Indicators
2.12 EXTERNAL CONNECTIONS
a
2.3 THE LOGIC COMPONENTS .. 2. 1 1 1 ww ee
TT
CONTENTS (CONT)
Page
CHAPTER 3 — GENERAL SYSTEM OPERATIONS ....: 2... 2 ee ee ee es 3-1
3.1 INTRODUCTION . 21 2 3-1
3.2 APPLYING POWER . 1 www we ee 3-1
3.3 PATCH PANEL INSTALLATION AND REMOVAL ........--- ++ +s 3-1
3.4 RUNNING ATYPICAL PROBLEM .. ww ww ee es 3-2
3.4.1. Introduction 2. 2 2. we 3-2
3.4.2 Preliminary Procedure... 1... we ee ee 3-2
3.4.3 Analog Initializing Procedures . . 2 1. 1. we ee 3-2
3.4.4 Logic Initializing Procedures. 2 ww ww ee 3-3
3.4.5 Testingthe Problem . . 2... 1 1. we ee 3-3
3.4.6 Dynamic Solution . . 2... 2. ee ee ee 3-3
3.5 RECORDING PROCEDURES ..... ee 3-4
3.5.1 Static Readout 2... ee 3-4
3.5.2 Dynamic Recording and Monitoring . 2... 2... 1 ek ee ee 3-4
3.6 AMPLIFIER BALANCING ........-..0.-. 000. ee eee ee ee 3-4
3.7 USING THE PROGRAM SHEET... 2... 1 1 35
PART Ii — USERS GUIDE (FOR THE INFREQUENT USER OR TRAINEE)
CHAPTER 4— INTRODUCTION TO USERS GUIDE .............0.68..002. 0484 4-1
4.1 USERSGUIDE .. 2.2... 4-1
4.2 GLOSSARY OF TERMS AND COMPUTING ELEMENTS .............. 4-1
CHAPTER 5 — PATCHING AND SETTING UP MATHEMATICAL FUNCTIONS .........., 5-1
5.1 INTRODUCTION . 2... ee 5-1
5.2 INVERSION 2... 5-1
5.3 SUMMATION .. 2. 2 5-1
5.4 INTEGRATION ... 2... 5-5
5.5 MULTIPLICATION AND DIVISION .. 2... ee, 5-5
5.5.1 Introduction 2... 2 2. 5-5
5.5.2 Product of Variableand Constant ... 2... .........,..2022.., 5-6
5.5.3 Productof Two Variables 2 2... 5-6
5.5.4 Division 2. 2... 5-7
CONTENTS (CONT)
Page
CHAPTER 5 — PATCHING AND SETTING UP MATHEMATICAL FUNCTIONS (Cont). ......
5.6 SQUARING AND SQUARE ROOT EXTRACTION .... 2... 64 2 eee eee 5-7
5.7 LOGARITHMS/EXPONENTIAL FUNCTIONS (FG Devices 16,26) .........-. 5-8
5.7.1 Natural Logarithm 2... 6 ee es 5-8
5.7.2 Exponential (e~'°%) 2 2. 5-9
5.8 CONSTRAINTS(LIMITS) 2... 2 5-10
5.9 SWITCHING FUNCTIONS ............ ee 5-11
5.9.1 Manual Switching .. . 2... ee ee ee . 5-11
5.9.2 Automatic Switching . . 1. 1. 2 we ee ee ee 5-11
5.10 CONSTANT VALUES ......- 2... ee ee ee 5-14
CHAPTER 6 — SETTING AND READING COEFFICIENT VALUES ............ wee. 61
6.1 INTRODUCTION ...... we ee tt ee 6-1
6.2 THE DIGITAL VOLTMETER AND POT CONTROLS ..... 2... 2. ee eee 6-1
6.3 PROCEDURE FOR SETTING APOT .... 1... ee ee es 6-1
6.4 PROCEDURE FOR READING POT VALUES ........ 2.2. eee ee eee 6-2
CHAPTER 7 — ARBITRARY FUNCTIONS FROM EMPERICALDATA ...........4.4.. 7-1
7.1 INFRODUCTION . 2. 1 ww 7-1
7.2 VFG THEORY ... 1. 7-1
7.3. THE VFG (Devices 36and37). 0... ee 7-1
7.4 SET-UPPROCEDURE ........ 2... 2.55.6. 50 4 2 eee rr 7-3
7.4.1 11PT(10SEGMENT) MODE ...... 2... 2 ee ee 7-3
7.4.2 20PT(19SEGMENT) MODE .... 2... ee ee 7-4
7.5 VFG PATCHING . 2.1. Le 7-5
CHAPTER 8 — CHECKING THE ANALOG PROGRAM... .. . Ln ee ee 8-1
8.1 INTRODUCTION ...........2084 Ce 8-1
8.2 STATIC CHECK THEORY ...... Lone ee ee Co 8-1
8.3 PROGRAM SHEET ...............+8. Coe 8-1
8.4 STATIC CHECK PROCEDURE .... 2... ee 8-1
CONTENTS (CONT)
Page
CHAPTER 9 — OBTAINING RESULTS USING AN X-YPLOTTER ........-.-+-2+ +25 9-1
9.1 INTRODUCTION 2... we - + 9-1
9.2 MiniAC TOEAI PLOTTER ..... 2... 2. ee 9-1
9.2.1 Connector Locations ... 2... ee 2. es OF
9.2.2 XM Versus Y Plotting . 2... 1... 2 ee ee ee ee ee OF
9.2.3 YVersusT Plotting . 2... 2... . . 92
9.3 MiniAC TO NON-EAI PLOTTER ... 1... ee «93
9.4 CALIBRATION . 2. 1. 2 ee 9-3
CHAPTER 10 — OBTAINING RESULTS USING AN OSCILLOSCOPE AND HIGH-SPEED
REPETITIVE OPERATION... ... 2... 2. 2 ee ee ee es -. . . . 10-1
10.1 INTRODUCTION .. 1. 2... 10-1
10.2.) REP-OP 2... 1... 10-1
10.3. THETIMER .... 2... 2.2... 2 10-1
10.4 MiniACTOEAISCOPE ....... 2. ee es 10-2
10.5 MiniACTONON-EAISCOPE .........-202. 2.000 eee ee 10-2
CHAPTER 11 — LOGIC AND ITERATIVE OPERATION ...........-..0 0082 2 eae 11-1
11.1. INTRODUCTION . 2... . ee . 17-1
11.2. LOGIC CONTROL OF ANALOG MODES ............0. 0.0824 2G -11-1
11.2.1 Overload Detection . 2... we .11-1
11.2.2 Three-Mode Repetitive Operation ........... 0.002 eee .11-1
11.2.3 Master Mode Control by Logic Signals . ...........20242. .11-2
11.2.4 Local Mode Control by Logic Signals . . 2... 2... wee ew 211-3
11.2.5 Mode Control Priorities 2... 2... ee . 11-4
11.3 LOGICDEVICES ............0... 2.000020 0 0G woes 11-4
11.3.1 AND,OR,NOTGates .... 2... 2.2.2.0... 2.0004 soe eee 17-4
11.3.2 Flip-Flops 2... ee 11-7
11.3.3 Shift Register... 1... ee 11-9
11.3.4 Binary Counting . 2... 11-11
11.3.5 Logic Timing .. 2... ee 11-12
11.3.6 Switching Logic Levels . 2. 2... 2... el, 11-13
11.4 ANALOGMEMORY ...........0.0.. 0.0.00 000002000, 11-14
11.4.1 TheT-SUnit 2... 2... ee, 11-14
11.4.2 Parameter Sweep Program. 2... 11-15
CONTENTS (CONT)
Page
11.4. ANALOG MEMORY (Cont)
- 11.4.3 Parameter Implementation. 2. 2. 2 2 6 ek 11-17
11.4.4 Boundary Value Problem ....... ee 11-21
CHAPTER 12 — EXAMPLE OF AUTOMATIC ITERATIVE OPERATION (A TWO-POINT BOUNDARY
VALUE PROBLEM)... . 2 2 1) eee ee 12-1
12.1 THEPROBLEMSTATEMENT ......... 0.2.00 0 2 eee Loe ee 12-1
12.1.1 Introduction 2... . . 212-1
12.1.2 Equations . 2... ee ee 12-1
12.1.3 Values. 2 1 . .12-2
12.2 PROCEDURE... . 2... 1 12-2
12.2.1 Preparing the Simulation 2... 6 6 1 we ee ee 12-2
12.2.2 Scaling 2 2. we 12-5
: 12.3. CHECKING THE PATCHED PROGRAM ....... 2... 2. eee eee ee 12-6
12.3.1 Static Test 2 2 2. ee 12-6
12.3.2 Logic Test 2. 2. 1 1 we 12-6
12.3.3 Dynamic Check . 2. 2 2. ee 42-7
12.4 RUNNING THE PROGRAM ...... 1. ee 12-7
PART IIl - REFERENCE HANDBOOK (FOR THE EXPERIENCED USER)
CHAPTER 13 — INTRODUCTION TO REFERENCE HANDBOOK ..........2...... 13-1
CHAPTER 14 — ANALOG MODE AND TIME SCALE CONTROL ................ 14-1
14.1 INTRODUCTION . 2... 14-1
14.22 THEANALOG MODES ...... 2... ee 14-1
14.2.1 SetPot (SP) 2... 14-1
14.2.2 Initial Condition (IC) 2 ww 14-1
14.2.3 Hold(H) 2... 14-1
14.2.4 Operate(OP). 2 14-1
14.2.5 Override Hold (ORH) .. 2... 2... 14-2
. 14.3, THETIMESCALES .... 2... , 2... .14-2
14.4 PUSHBUTTON MODE AND TIMESCALE CONTROL ............... 14-2
CONTENTS (CONT)
Page
CHAPTER 14 — ANALOG MODE AND TIME SCALE CONTROL (Cont)
14.5 PATCH PANEL MASTERMODE CONTROL .............-+ ++ 0 + 14-3
14.5.1 General Operation . 2... 2. 14-3
14.5.2 The Input Control Terminations . 2...) ee es . 14-3
14.5.3 The Output Terminations . 2... 14-4
14.5.4 Selecting Patch Panel Mode Control . . 1... . . 144
14.5.5 Repetitive Operation ........202.2020 2. 2. ee hee ee . 14-4
14.5.6 Iterative Operation . 2... ee 14-6
14.5.7 Override Hold and Overload Store Operations .......2.2.....-. . 14-6
14.6 LOCAL PATCHPANELCONTROL ................. 0.00084 14-9
14.6.1 Introduction 2. 2... ee ee 14-9
14.6.2 Locat Control of Integrators 2... 2. le 14-9
14.6.3 Local Control of T-S Amplifiers . 2... ..0..2.02022.2. 2.02854. . 14-10
14.7, COMPUTER SLAVING AND ANALOG TRUNKS ................ 14-11
CHAPTER 15 — LOGIC CLOCK AND LOGIC MODE CONTROL ..............0~2... 15-1
15.4 INTRODUCTION . 2... 2. 15-1
15.2 THELOGICMODES ...............0.2.00.2. 0002.00, . . 15-1
15.2.1 Run... 2 15-1
15.2.2 Stop/Step (STP) 2... 2. ee tt ee 15-1
15.2.3 Clear(CLR) 2... ee 15-1
15.3. LOGICMODECONTROL ...........0...0.0 00000000084 . 15-1
15.4 THE CLOCK DOWNCOUNTER (PULSES) ..................0..,4 15-2
CHAPTER 16—THESIGNALSELECTOR ...............2..0..2..0-. 0048, 16-1
16.1 INTRODUCTION ..........0.0..0...00. re 15 |
16.2 READOUT OF ADDRESSABLE COMPONENTS ................ . 16-1
16.3 THEDVMDISPLAY...........0.0.0. 000.000.000.000 0020, 16-2
16.4 THESELECTORTERMINATIONS .............0....2., . ee. . 16-2
16.4.1 Selector Tand2 . 2... td, rs . .16-2
16.4.2 Selector — MTR IN
CHAPTER 17 — THE OVERLOAD AND STATUS INDICATORS |
17.1
17.2
17.3
17.4
CONTENTS (CONT)
INTRODUCTION
THE OVERLOAD INDICATOR SYSTEM
17.2.1 Overload Criteria
17.2.2: The Overload Indicators
17.2.3 Logic Level and Control
ANALOG STATUS INDICATORS
17.3.1 Introduction . . 2... Lo ee
17.3.2 Comparator Indicators
17.3.3 Time Scale fndicator . . . .
17.3.4 Analog Mode tndicators
LOGIC STATUS INDICATORS
CHAPTER 18 — COEFFICIENT POTENTIOMETER . .
18.1
18.2
18.3
CHAPTER 19 — FIVE-INPUT SUMMER/HIGH GAIN AMPLIFIER
19.1
19.2
19.3
19.4
LOCATION AND IDENTIFICATION
THE POTENTIOMETER
POTENTIOMETER SET-UP AND MONITORING
LOCATION AND IDENTIFICATION
THE AMPLIFIER
USED AS A SUMMER
USED AS A HIGH-GAIN AMPLIFIER
CHAPTER 20 — SUMMER/TRACK-STORE AMPLIFIER
20.1
20.2
20.3
20.4
LOCATION AND IDENTIFICATION
THE T-S AMPLIFIER
20.2.1 Introduction
20.2.2 Mode Control
USED ASASUMMER ........
USED AS A TRACK-STORE UNIT
Page
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17-1
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19-1
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. 20-1
. 20-3
.20-3
CONTENTS (CONT)
CHAPTER 21 —SUMMER/INTEGRATOR .....
21.1 LOCATION AND IDENTIFICATION
21.2 THE SUMMER/INTEGRATOR
21.3 USEDASASUMMER .......,....
21.4 USED AS AN INTEGRATOR
21.5 USED AS A TRACK-STORE AMPLIFIER
21.6 USING THE 10 SW CONTROL INPUTS
CHAPTER 22—LIMITERS .........
22.1 LOCATION AND IDENTIFICATION .....
22.2 THE FEEDBACK LIMITER .....
22.3. USING THE LIMITER ........,
22.3.1 Patching
22.3.2 Limiter Set-Up Procedure
CHAPTER 23 — MULTIPLY/DIVIDE UNIT
23.1 LOCATION AND IDENTIFICATION
23.2. THE MULTIPLIER
23.2.1 Introduction
23.2.2 Multiplication, Squaring and Square Root
23.2.3 Division
23.2.4 Summation
23.3. USING THE MULTIPLIER
CHAPTER 24 — LOG/EXPONENTIAL GENERATORS
24.1 LOCATION AND IDENTIFICATION
24.2 THE FUNCTION GENERATOR
24.2.1 Introduction
24.2.2 Logarithms .
24.2.3 Exponential Functions (Antitogarithms)
24.2.4 Summation
24.3. USING THE FUNCTION GENERATOR
viii
Page
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23-1
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23-1
. 23-2
24-1
24-1
24-4
24-1
24-1
24-2
24-2
24-3
CHAPTER 25 — VARIABLE FUNCTION GENERATOR
25.1
25.2
25.3
25.4
25.5
25.6
25.7
CONTENTS (CONT)
LOCATION AND IDENTIFICATION
THE VFG
25.2.1 General Operation . .
25.2.2 Modes of Operation
25.2.3 The VFG Controls
HOW TO SET UP THE VFG
25.3.1 Tabulating Values of X and Fey
25.3.2 Determining Breakpoint Location
25.3.3 VFG Setup Theory
SETTING AN 11-POINT FUNCTION . .
25.4.1 General
25.4.2 Preliminary Setup Procedures
25.4.3 Setting X and Y . .
25.4.4 Insufficient Slope
25.4.5 Trimming Adjustments .
SETTING A 20-POINT FUNCTION
PLOTTING THE FUNCTION .....,
PATCHING THE VFG INTO A PROBLEM
CHAPTER 26—ANDGATES. .
26.1
26.2
26.3
CHAPTER 27 — GENERAL PURPOSE AND PUSHBUTTON FLIP-FLOPS
27.1
27.2
27.3
LOCATION AND IDENTIFICATION
THE AND GATE
USING THE AND GATE
LOCATION AND IDENTIFICATION
THE PUSHBUTTON FLIP-FLOP
THE GENERAL PURPOSE FLIP-FLOP .
27.3.1 General Operation .
27.3.2 The Pushbutton Control
27.3.3 The Patch Panel Terminations
Page
25-1
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. 26-1
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.27-1
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CHAPTER 27 — GENERAL PURPOSE AND PUSHBUTTON FLIP-FLOPS (Cont)
27.4
CONTENTS (CONT)
BASIC CIRCUITS USING THE GPFF
27.4.1 GeneralUse 2... 2...
27.4.2 Used to Generate a One Clock Delay
27.4.3 Used as a Differentiator
27.4.4 Using the Latching Function
27.4.5 Used as a Flip-Flop Register
CHAPTER 28 — ANALOG SWITCHES AND COMPARATORS
28.1
28.2
28.3
28.4
LOCATION AND IDENTIFICATION
THE MANUAL SWITCH
THE D/A SWITCH
28.3.1 General Operation .
28.3.2 Using the D/A Switch
THE A/D COMPARATOR
28.4.1 General Operation . .
28.4.2 Basic Comparator Patching
CHAPTER 29— TIMING DEVICES .....
29.1
29.2
29.3
29.4
LOCATION AND IDENTIFICATION
THE INTERVAL TIMER
29.2.1 Overall Operation
29.2.2. The Manual Controls
29.2.3 The TIMER Patch Panel Terminations
29.2.4 Using the Timer .
THE COUNTER/TIMER
29.3.1 General Operation . .
29.3.2 The Manual Controls
29.3.3 The Patch Panel Terminations. -
29.3.4 General Use
29.3.5 Used as an Event Counter
29.3.6 Used as an Event Monitor
29.3.7 Used as a One-Shot
29.3.8 Used as a Logic Timer
THE MONOSTABLE MULTIVIBRATOR
Page
.27-3
.27-3
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.28-1
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- 28-2
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.29-1
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. 29-2
. 29-3
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.29-7
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. 29-9
.29-9
. 29-10
. 29-12
. 29-12
Figure
Number
17
217
2.2
2.3
24
25
2.6
2.7
37
5.7
5.2
5.3
5.4
5.6
5.6
5.7
5.8
5.9
5.10
5.17
6.1
7.4
7.2
7.3
7.4
8.1
8.2
8.3
8.4
9.7
9.2
9.3
ILLUSTRATIONS
Title
Typical MiniAC Computing System
Typical MiniAC
The Patch Panel
General Patching Areas
DVM and Coefficient Pot Panel .
Analog Control Panel
Logic Contro/ Panel .
Setup Switch/Overload Indicator Panel (Open}
Program Sheet
Inversion: Patching and Setup
Summation: Patching and Setup
Integration (With Initial Condition): Patching and Setup
Multiplication of Variable and Constant: Patching and Setup
Multiplication of Two Variables: Patching and Setup
Division: Patching and Setup .
Square Root: Patching and Setup
Natural Logarithm
Exponential Function
Constraints: Patching and Setup
Programmed Switches: Patching and Setup .
DVM and Coefficient Pot Controls
Sample Arbitrary Function . .
The VFG Controls
Program for Plotting VFG Output .
VFG Patching
The Programming Process and Passible Errors
Sample Program Sheet .
Sample Problem
Selector: Patching Area and Controls
Typical Patching for X Versus Y Plot
Typical Patching for Y Versus T Plot
Sample Plotter Calibration
Page
1-1
. 22
. 24
. 2-6
.2-10
2-17
.2-14
.2-16
. 37
. 5-2
. 5-4
. 55
. 56
. 5-6
. 57
. 5-7
. 58
. 5-9
. .5-10
.§-13
7-1
_ 7-2
7-4
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. e7
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. b3
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. 91
9-2
9-4
xi
xil
Figure
Number
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
14.1
14.2
14.3
14,4
14.5
14.6
15.1
16.1
16.2
17.1
18.1
19.1
19.2
19.3
20.1
20.2
20.3
21.1
21.2
21.3
21.4
21.5
ILLUSTRATIONS (CONT)
Title
Shift Register Operation
Logic Counter
The Track-Store Unit
Track-Store Behavior
Parameter Sweep: Basic Program and Waveforms
Parameter Sweep: Patching
Parameter Implementation with an Integrator
Parameter [mplementation with a Counter
Analog Mode and Time Scale: Controls and Patching Areas
Typical Repetitive Operation: Patching and Timing
Typical Three-Mode Iterative Operation: Patching and Timing .
Basic ORH and OLS Patching .
Integrator Mode and Time Scale: Local Control Patching
Track-Store: Local Control Patching
Logic Clock and Logic Mode: Patching Areas and Controls
Readout Controls and Patching Areas
Signal Selector System: Simplified Diagram
Overload and Status Indicator Locations
Potentiometer: Circuit and Symbol
Summer/High Gain: Simplified and Equivalent Circuits
Summer Patching: &/HG Switch Released (Out)
High-Gain Patching: X/HG Switch Set (In)
Summer/Track-Store: Simplified and Equivalent Circuits
Typical Track-Store Operation
Basic Track-Store Patching
Summer/integrator: Simplified and Equivalent Circuits
Summer Patching: &/f Switch Released (Out)
Integrator Patching: 2/f Switch Set (In)
Patching the 2/f as a Track-Store Amplifier: 2/f Switch Set {in}
Gain —10 Switching .
Figure
Number
22.1
22.2
22.3
23.1
23.2
24.1
24,2
24,3
24.4
24.5
25.1
25,2
25,3
25.4
25.5
25.6
25.7
25.8
26.1
26.2
26.3
26.4
27.1
27.2
27.3
27.4
27.5
28.1
28.2
28.3
28.4
ILLUSTRATIONS (CONT)
Title
Simplified Limiter Circuit: Used with Typical Amplifier
Limiter: Patching and Equivalent Circuit . . .
Limiter Setup
Multiply/Divide Unit: Simplified Circuit
Multiply/Divide Unit: Setup and Patching
Log/Exponent Function Generator: Simplified and Equivalent Circuits
The Logarithmic Curve (0.1 Inx). 2. 0. ww kk ee ee
The Exponential (Antilog) Curve (e°1°*)
Log/Exp Function Generator: Setup and Patching ........
GeneratingX” |... 0...
VFG: Controls and Patching Area
Typical Diode Segment
VFG Modes and Equivalent Circuits
Sample Ten Segment Function .. 2... 0... ee
Effect of Changing Slope Pot Y6 on VFG Output
Sample 19 Segment Function .
Typical Setup for Plotting A Function
VFG: Basic Patching
Gates: Simplified Circuits
Gate Patching
Typical AND Gate Fan-Out Circuit
Typical Method of Cascading Gates
The Pushbutton Flip-Flop
The General Purpose Flip-Flop
GPFF. Basic Patching and Operating Information
GPFF: Patching and Timing
Using the GPFF to Form a Register
Manual Switch: Patching and Operating Information
D/A Switch: Patching and Operating Information
The Comparator
Comparator Patching
xii
xiv
Figure
Number
29.1
29.2
29.3
29.4
29.5
29.6
29.7
29.8
29.9
ILLUSTRATIONS (CONT)
Title
The Interval Timer
Typical Use (Run and H Unpatched): Timer Starts when PP is Depressed
Typical Use of RUN: Delayed Start
Typical Use of H: Extended B (OP) Interval
The Counter/Timer
Event Counter: Patching and Timing . .
One-Shot: Patching and Timing
Frequency Divider: Patching and Timing
The MONO
Page
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29-4
29-6
. 29-6
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. 29-13
Table
Number
2.1
2.2
2.3
2.4
2.5
2.6
2.7
14.7
14,2
14.3
15.1
16.1
25.1
25.2
29.1
29,2
TABLES
Title
Equipment Complement: Analog Components
Equipment Complement. Logic Components
Equipment Complement: Analog/Logic Interface Components .
Patch Panel Field Assignments for Analog Components
Analog Control Panel: Controls and Indicators
Logic Control Panel: Controls and Indicators
Setup Switch Functions
Shift Register Operation .
The Time Scales .
PP Master Mode Truth Table
Master Mode Patch Panel Outputs
Clock Downcounter: Output Frequencies and Periods
Device Addressing (SELECTOR-1) .
11-Point Table of Values .
Sample Order of Procedure (Ten-Segment Function)
Timer Range Versus SECONDS Switch Setting
Timer Patch Panel Terminations
Page
24
. 23
. 2-3
27
2-11
2-14
2-17
11-9
14-2
14-3
14-4
15-3
16-1
25-7
25-8
29.2
29-2
XV/XVI
a,
Figure 1.1 Typical MiniAC Computing System
CHAPTER 1
ee
INTRODUCTION
1.1. THE EAI MiniAC™ (Figure 1.1)
The EAI MiniAC is an educational analog/hybrid simulation system specifically designed for technical colleges,
university engineering and science departments, and industrial training groups. Peripherals that can be used with the
MiniAC include an X-Y Plotter, and a display scope.
The MiniAC Console is the major system component and is a self-contained 10 volt reference analog computer. This
computer contains analog and logic computational components, control logic, hybrid (analog/logic interface)
components, and operating controls. A basic system can solve a non-linear second-order differential equation with an
imposed limit and has provisions for an analog comparison and logical operation. A fully expanded system can solve an
automatic optimization and plot two to three non-linear third order differential equations. Problems are introduced at a
removable patch panel; the removable feature permits storage of programmed problems.
1.2 PURPOSE OF MANUAL
This manual ts written with three specific goals in mind:
1. To familiarize a/f users with the computer organization and patching facilities, the basic functions of the
various operating controls and indicators, and the general operation of the system as a whole.
2. To provide a guide for the occasional user or trainee that allows him to patch and run his particular problem
without delving into circuit related details.
3. To provide the relatively experienced user those details that will permit him to utilize the MiniAC to its
fullest extent.
1.3 STRUCTURE OF MANUAL
To achieve the above goals, this manual is divided into three separate and distinct parts as follows:
PART 1— FAMILIARIZATION AND GENERAL OPERATION
PART 2— USERS GUIDE
PART 3— REFERENCE HANDBOOK
Each part of this manual is divided into three or more chapters. All chapters are numbered consecutively within a part,
and from part-to-part.
PART 1— FAMILIARIZATION AND GENERAL OPERATION
Is oriented toward all users and consists of Chapters 1 through 3. Describes the overall system, locates and
identifies all major components, and contains general operating information for the computer as a whole. The
user should be completely familiar with PART 1 before attempting to use the MiniAC or before proceeding to
either PART 2 or 3.
PART 2— USERS GUIDE
Consists of Chapters 4 through 12. This portion of the manual is directed at the infrequent user and/or the
trainee. Part 2 is oriented toward problem solving and carries the user from patching and setting up the simplest
mathematical function all the way up to patching and running a sample two point boundary value problem.
1-1
1-2
PART 38 - REFERENCE HANDBOOK
The reference handbook portion of this manual (Chapters 13 through 29) is directed toward the frequent or
relatively experienced user. Part 3 describes in detail the workings of the MiniAC subsystem by subsystem and
component by component. Sufficient information is provided to permit the experienced programmer to fully
utilize all programmable features to devise unique patching schemes on a subsystem and an individual component
basis.
1.4 HOW TO USE THIS MANUAL
First, read Part 1 to become thoroughly familiar with the organization of the machine, the patch panel, the basic
function of the various controls and indicators, and the general operating procedures. Then, if reasonably on board with
Analog Programming and analog computers in general, refer to the reference handbook portion of the manual. If this is
your first introduction to an analog computer or you have seldom used one, it is advisable to proceed directly to the
Users Guide. In either case (experienced or trainee), a cursory review of the Table of Contents will aid you in locating
specific information required to patch and run your particular problem.
CHAPTER 2
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MACHINE ORGANIZATION
2.1. INTRODUCTION
This chapter provides information to acquaint the user with the appearance, location, and basic functions of major
components of the EA! MiniAC. Figure 1.1 illustrates a typical system with peripheral devices. The MiniAC is the heart
of the system and contains all necessary analog programming facilities, computing elements, control features, and basic
monitoring devices. All uncommitted programmable components are terminated at the patch panel and are
interconnected with patch cords as required by the specific program. The peripheral devices permit the operator to
interact with the master program and graphically record or document instantaneous problem solutions. The following
paragraphs give a brief description of those portions of the console (Figure 2.1) that are of prime importance to the
programmer/operator.
2.2 THE ANALOG COMPONENTS
A fully expanded MiniAC provides an array of analog computational devices. Table 2.1 lists the analog equipment
complement provided with a fully expanded MiniAC. This table also includes specific chapter references in which each
component is described. With the exception of the manual switches, coefficient potentiometers, and the variable
function generator, all analog components that perform mathematical functions are located directly behind the
setup switch/overload indicator panel.
Table 2.1. Equipment Complement: Analog Components
Chapter Reference
Component Quantity
Users Guide Reference Handbook
Linear (Including those associated with
multipliers, function generators, etc.):
Summer/Integrator {2//) 6 5 21
Five-Input Summer/High Gain (=) 3 19
Five-Input Summer/Track Store ({/TS) 3 20
Two-Input Summer/Inverter (MULT/DIV) 3 23
Three-Input Summer (FG) 2 24
Inverter (VFG) 2 5 25
Potentiometers 18 5,6 18
Non-Linear:
Multiplier (MULT/DIV}: 3 5 23
Function Generators:
Log/Exponential 2 5 24
Variable (10 Segment) 2 7 25
Interval Timer: 1 9,10 29
Manual Switches: 3 5 28
Trunks: 12 - 14
Digital Voltmeter (DVM) 1 6 16
2-1
DVM AND
COEFFICIENT VFG
PATCH PANEL POT PANEL COVER PANEL
/
SETUP/ LOGIC CONTROL ANALOG CONTROL
OVERLOAD INDICATOR PANEL PANEL PANEL
Figure 2.1. Typical MiniAC
2.3. THE LOGIC COMPONENTS
The various logic elements available for use in the MiniAC provide operational flexibility to physical system simulation.
These logic elements permit simulation of descrete and continuous systems and provide a wide range of flexibility in
problem control. In other words, a logical event can be used to control an analog function and vice versa. All logic
elements (such as pushbutton flip-flops, general purpose flip-flops, and the counter/timer} are physically located
directly behind the logic control panel (Figure 2.1). Table 2.2 lists the equipment complement provided with the logic
expansion and specifies the chapter(s) in which each component is described.
Table 2.2. Equipment Complement: Logic Components
Component Quantity Chapter Reference
Users Guide Reference Handbook
Gates:
Two Input 6 11 26
Four Input 4
Counter/Timer: 1 11 29
Flip-Flops:
General Purpose 4 1 27
Pushbutton 2
Monostable Multivibrator (One Shot): 1 11 29
2.4 THE ANALOG/LOGIC INTERFACE COMPONENTS
Analog/logic interface components provide interface and control between the analog and logic portions of a program.
These devices include analog controlled digital (A/D) comparators and digital controlled analog (D/A) switches.
The equipment complement of analog/logic interface components is listed in Table 2.3. This table also includes specific
chapter references in which these devices are described. Like the analog and logic components, these hybrid devices are
terminated at the patch panel.
Table 2.3. Equipment Complement: Analog/Logic Interface Components
Chapter Reference
Component Quantity
Users Guide Reference Handbook
A/D Comparators: 3 5 28
D/A Switches:
Uncommitted (SW) 3 5 28
Summer/Integrator Committed (10SW) 12 5 21
2-3
‘
ANALOG FIELD 1
CONTROL FIELD
ANALOG FIELD 3
11 12 13 14 15 16 CONTROL 31 32 33 34 35 36/37
r/f r/f >») z/TS MULT/DIV FG a z/f z/f >» z/TS MULT/DIV VEG
Sw_JUmTR | MAN sw SELECTOR [L_bDisPtay _] SW_JUMTR| MANSW
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or MTR START
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ANALOG FIELD 2
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LOGIC FIELD
2.5 THE CONTROL AND MONITORING SYSTEMS
The MiniAC is equipped with versatile control and monitoring systems that permit: selection of addressable analog
components for value readout and display; control of analog time scale; control of analog and logic modes; and slave
Operations. Complete monitoring facilities are provided that permit status readout of logic elements as well as indicating
amplifier overload conditions. All aspects of these systems are described in Chapters 14 through 17 of the Reference
Handbook.
2.6 THE PATCH PANEL
2.6.1 INTRODUCTION
The following paragraphs describe the patch panel layout. This includes: general patch panel location of individual
components and controls; the component location numbering system (address); and general color coding information.
Detailed information concerning patch panel layout for individual components and controls (including patching
techniques and methods) are given in subsequent chapters describing the specific component or control system.
The removable panel (Figure 2.2) provides readily accessable termination and interconnection points for assembling
(patching) devices that perform mathematical and logical functions in any array required to obtain a given problem
solution. The patch panel also provides patching facilities for problem contro! purposes and problem solution outputs.
Patching is the act of interconnecting the mathematical and logical elements so that the assembled (patched) devices
correspond to the “‘paper’’ program. Patching may be performed with the panel on the computer, or “‘off-line’’. If more
than one patch panel is available, a problem may be prepatched {remotely from the machine) while another problem is
being run. In other words, one user can produce a problem solution while another is preparing a problem. The
availability of multiple patch panels permits retaining (storing) a patched problem or simulation that may be used
frequently for demonstration or other purposes,
2.6.2. PATCH PANEL LAYOUT
2.6.2.1 General
For ease in programming and locating components for patching, the MiniAC patch panel is divided into symmetrical
fields, Basically, there are three nearly identical analog fields, an analog trunk field, a logic field, and a contro! field.
Each field is distinct and readily identified. Figure 2.3 is a simplified diagram of the patch panel and shows the general
patching outlines and areas associated with each field. As an aid in identifying the various patching areas, compare this
illustration to the patch panel details shown in Figure 2.2,
2-5
2-6
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PULSES 109 - C2 MONE
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21 22 22 24 25 26 ' |
ANALOG FIELD 2--- --- --— —+ CONTROL FIELD -———-#fe—- = LOGIC FIE.2 a -. Ww
SYMBOLS AND ABBREVIATIONS
7 =INTEGRATOR += PLUS TEN OL? REFERENCE (+ 1.000 MACHINE UNIT] 1= LOGIC LEVEL ONE(+5V1 MONG + MONQS TABLE MULTIVIBRATOR
= = SUMMER
TS = TRACK-STORE
Ov= OPERATE JUNCTION (E//)
SJ = SUMMING JUNCTION (Z OR E/ TS)
POT = FOTENTICME TER
COMP = COMPARATOR
— = MINUS TEN VOLT REFERENCE (- 1.000 MACHINE UNIT}
+ LOGIC LEVEL CEROILOGIC GRDI PBFE = FUSKSOTTON FLIP-FLOP
MAN SW=MANUAL SWITCH
MULT/DEV = MULTIPLY / BIVIDE
Sw: DIGITAL CONTROLLEO ANALOG SWITCH
FUN > FUNCTION GENERATOR
GEN
Figure 2.3. General Patching Areas
2.6.2.2. The Analog Fields
Basically, each analog field is divided into six rectangular patching areas, or modules. Each module provides
terminations for at least two analog components. For patching convenience, each module includes terminations for a
potentiometer, and computer reference (+1.0 machine units) is distributed throughout each field,
A two digit number embossed on the patch panel identifies the patching module and the field. The first digit (1-3) is
the field designation. The second digit is the assigned modute number (1-6). For example, the fifth patching module in
field one is assigned the number 15 (field 1, module 5), Therefore, anatog components terminated in this field/module
are identified by the number 15.
In addition to the field/module numbering system, modules are further identified by a symbol or mnemonic
designation that indicates the major computing component terminated in that module, For example, modules 1 and 2
in each field are marked with the Y// symbol (Figures 2.2 and 2.3). This indicates that the major computing
component terminated in these modules is the summer/integrator. Table 2.4 lists each component and facility
terminated in the patch panel analog field, identifies each by symbol or mnemonic designation and module number,
and lists the quantity per field.
Table 2.4. Patch Panel Field Assignments for Analog Components
Symbol Quantity Per Field
or Mnemonic Module
Analog Component or Facility Panel Marking Number 1 2 3 Totals
Summer/Integrator =/f 1,2 2 2 2 6
Summer/High Gain >> 3 1 1 1 3
Comparator COMP 3 1 1 1 3
Summer/Track Store L/TS 4 1 1 1 3
Multiplier MULT/DIV 5 1 1 1 3
Digital Controlled Analog Switch SW 5 1 1 1 3
Limiter LMTR 5 1 1 1 3
Log X Function Generator FG 6 1 1 0 2
Manual Switch MAN SW 6 1 1 1 3
Variable Function Generator VFG 6/7 0 0 2 2
Potentiometer None 1-6 6 6 6 18
(Colored
coded
yellow)
Positive Reference + 1-4,6 5 5 5 16
Negative Reference _ 1-4,6 5 5 5 15
Analog Ground None N/A 0 0 8 8
(Color
coded
black)
To simplify the process of patching a problem, the analog fields use a readily identifiable color code. The principle
colors used are green, red, orange, yellow, white and black.
Green = Analog component inputs,
Red = Analog component outputs and positive reference.
Orange = Minus reference
Yellow = Potentiometers
White = Passive element manual switches and limiters
2-8
2.6.2.3. The Trunk Field
The trunk field is located between analog fields one and two and is identified by the designation TRUNKS. These
terminations provide 12 general purpose trunk lines for exchanging analog data with another computer or for use with
external analog devices.
2.6.2.4 The Logic Field
All logic computing elements are terminated in the patching area directly below Analog Field 3 (Figures 2.2 and 2.3}.
Logic component terminations are contained in a separate field to minimize cross-talk (noise pick-up) and to reduce the
possibility of inadvertently patching an analog signal to a logic component, or vice versa.
The logic field has provisions for program patching of: AND gates, a counter/timer; general purpose and pushbutton
flip-flops, a monostable multivibrator, and down counted clock pulses. With the exception of AND gates, all logic
outputs on the patch panel are synchronized with the system clock. Each logic component is identified by panel
markings as indicated in the following list:
Logic Component Panel Designation Quantity
Gates: ’
Two-Input GATE 1 to GATE 6 6
Four-Input GATE 7 to GATE 10 4
Counter/Timer CTR/TMR 1
General Purpose Flip-Flops FF to FF4 4
Pushbutton Flip-Flops PB1 and PB2 2
Down Counted Clock PULSES (10°, 10%, 10°, 107) 4
Monostable Multivibrator (One Shot) MONO 1
To simplify the process of patching a problem, the logic field has a color code similar to that of the analog fields. The
colors used are green, orange, and red. These indicate the following:
Green = Logic inputs (1 = +5V; 0 = GRD)
Orange = Asynchronous {unclocked) logic outputs.
Red = Synchronous (clocked) logic outputs.
Red on White = Logic level output.
2.6.2.5 The Control Field
The control field (Figures 2.2 and 2.3) is the white patching area separating analog fields 1 and 2 from analog field 3
and the logic field. Primarily, the control field provides patching facilities to permit logic signals to be used for
individual component and computer mode control. The control field is functionally divided into three major areas as
follows:
1. Readout Selection and Control
2. Master mode Control
3. Local Control
The readout area is located in the uppermost portion of the control field and permits patching the readout selector to
external devices, as well as logic start/stop control of a remote display device (recorder or oscilloscope).
The inverted L shaped area below the readout termination group is devoted to logic control of computer modes. That
is, if the patch panel (PP) is selected as master, the 1C, H and OP modes can be selected by patching of logic signals. An
interval timer is terminated in this area to permit automatic repetitive operations.
The patch panel provides terminations that permit individual logic control of analog components terminated in analog
fields 1 through 3. Controlling individual analog components with logic levels patched at the control field is referred to
as local control. Local control functions that can be performed by patching include: integrator time scale and mode;
track-store/summer mode: D/A switch operation; and latch control of comparators. These logic control terminations
are divided into three identical groups {one for each analog field) and are identified using the field/module numbering
system described in Paragraph 2.6.2.2. To avoid confusion and for simplicity of patching, all local controls are marked
with the corresponding field/module number and are further identified by the applicable symbol or mnemonic
designation. As in the logic and analog fields, the control field is also color coded. However, in this case the panel
symbol or lettering is color coded, not the background. The color codes used are green, red, and black. These indicate
the fotlowing:
Green = Logic input in all areas. DISPLAY 1-7 and MTR-IN may also be used as analog inputs.
Red = Synchronous logic output or fixed logic level (0 = logic zero output).
Black = Analog ground.
2.7 DVM AND COEFFICIENT POT PANEL
The DVM and coefficient pot panel (Figure 2.4} contains the digital voltmeter (DVM) and the controls required to set
constant coefficients into an analog program. The DVM displays the numeric value (in machine units) of any
component selected for readout. Refer to Chapter 6 in the User’s Guide or Chapter 16 in the Reference Handbook
portion of this manual.
Problem coefficients are normally provided by the preset potentiometers mounted on this panel. These pots are
arranged in three vertical columns with six in a column. Each pot is terminated at the patch panel and is identified by
the numerical panel marking that corresponds to the patch panel address described in Paragraph 2.6. The individual pot
knobs are used to preset the desired coefficient value. The pushbutton switches immediately to the right of each pot are
used to display the pot output on the DVM. Pot setting procedures are given in Chapters 6 and 18 of the User’s Guide
and Reference Handbook respectively.
2-9
Figure 2.4. DVM and Coefficient Pot Panel
2.8 THE VFG PANEL
The variable diode function generator (VFG) is located directly behind the removable VFG panel (Figure 2.1). This
panel is only removed during set-up of the VFG and should remain in place at all other times to avoid inadvertently
disturbing the VFG setup. The VFG is described in Chapter 7 of the User’s Guide and Chapter 25 of the Reference
Handbook.
2.9 THE ANALOG CONTROL PANEL
The analog control panel (Figure 2.5) is located at the right side of the MiniAC directly below the VFG panel, This
control panel contains the power on switch; the computer analog mode controls; the time scale (rate) control; the
interval timer controls; the readout signal selector; manual switches and manual controls for the comparators. The ba