DO 910 Simulation System — Operator’s Manual

This document is an English translation of the original German-language Bedienungshandbuch (operator’s manual) for the Dornier-System GmbH DO 910 Simulationssystem.

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Table of Contents

1. Introduction
2. System Architecture
   • 2.1 System Overview
   • 2.2 Commodore CBM 8032
   • 2.3 Analog Section
   • 2.4 Interface
3. Description of the Basic Unit
   • 3.1 Controls and Indicators
   • 3.2 Interconnection of Subsystems
     • 3.2.1 General
     • 3.2.2 IEC Bus Particularities
     • 3.2.3 Correct Connections
4. Operating the System
   • 4.1 Switching On
   • 4.2 Program Input
   • 4.3 The DO 910 MONITOR
5. Summing Amplifier Module
6. Integrator Module
7. Multiplier Module
8. Potentiometers
9. Comparators
10. Function Switches
11. Limiters
12. Variable Diode Function Generator
13. Logic Components
14. Dead-Time Element

Appendix: IEC Transfers in BASIC

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1. Introduction

This manual for the DO 910 Simulation System serves two purposes: it provides guidance for the inexperienced user regarding programming and operation, and it serves as a reference for special circuits and programming techniques for the experienced user.

The manual describes a novel system that combines analog and digital computing techniques. A basic knowledge of analog computing on one hand and digital-computer programming in BASIC on the other is therefore assumed.

Those unfamiliar with analog computing are referred to the introductory literature on the subject. For the Commodore CBM 8032 computer, the user is referred to its own manual.

The DO 910 is built and tested in accordance with DIN 57411/Part 1 and VDE 0411/Part 1. It has left the factory in a technically safe condition. To maintain this condition and ensure safe operation, the user must observe all warnings and notices in this manual and in other technical documentation.

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2. System Architecture

2.1 System Overview

The DO 910 system consists essentially of three parts:

• The Commodore CBM 8032 computer with cassette deck
• The analog section with analog computing elements
• The interface between them

2.2 Commodore CBM 8032

This computer is one of the most widely distributed desktop computers. The DO 910 uses it in a 32 KB configuration. A cassette deck is included as standard. Subsequent expansion with Commodore-standard peripherals is possible. A disk unit (e.g. CBM 8050) and/or a printer (e.g. CBM 4022) is recommended for operation with the DO 910. Programming is in BASIC, whose interpreter is built into the CBM 8032.

2.3 Analog Section

The analog section of the DO 910 was developed from the DO 80 analog computer and contains largely the same components. The DO 80 is a compact analog computer proven in well over 100 diverse applications. The analog section contains 25 plug-in positions that can be populated with various modules:

• Up to 5 potentiometer plug-in units, each with: 4 hand potentiometers, 1 comparator, 1 limiter, 1 function relay, 1 function switch
• Up to 20 computing-element modules, selectable from:
  • 1 integrator (with electronic or relay mode control)
  • 2 summers + 1 multiplier/divider
  • 1 dead-time element
  • Adjustable function generators
  • 1 logic clock and 2 counters
  • Flip-flops and 1 monoflop
  • 5 AND/NAND gates

Because all these different modules can be combined in any mixture (the only restriction being no more than 20 modules in one DO 910 analog section), the resulting number of configuration variants is almost astronomical.

2.4 Interface

The interface is connected to the CBM 8032 via an IEC 625 (also known as IEEE 488) bus. It can therefore be operated together with other IEC-compatible devices (e.g. other Commodore peripherals) over a single bus, addressed via standard BASIC commands.

Part of the interface is intended for connection of the DO 910 analog section, or alternatively a DO 80 analog computer. Signals for controlling operating modes and time constants, and for reading overload and comparator status, are carried through this part.

The other part of the interface provides additional components whose inputs and outputs are accessible at 4 mm sockets on the interface front panel:

• 8 digital inputs
• 8 digital outputs
• 16 analog inputs
• 4 multiplying analog outputs (MDACs)

The interface can also be used independently of the analog section for data acquisition and process control.

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3. Description of the Basic Unit

3.1 Controls and Indicators

The DO 910 system, viewed from front and rear (with rear panel removed), has the following numbered elements:

1. Mains switch for the Commodore CBM 8032
2. Mains switch for the interface (and simultaneously for the analog section)
3. CBM 8032 computer with screen and keyboard
4. Cassette deck for the CBM 8032
5. Interface
6. Status LEDs for the analog operating modes
7. Connection sockets for the 4 multiplying D/A converters (upper row: inputs, lower row: outputs)
8. Connection sockets for the 16 analog inputs (multiplexer with downstream A/D converter)
9. Connection sockets for the 8 digital inputs (upper row) and outputs (lower row)
10. IEC 625 address switch for the interface — sets the device address under which the interface will be accessed
11. Connecting cable for signals to and from the analog section

3.2 Interconnection of Subsystems

3.2.1 General

Before switching on the system, the user must verify that the supply voltage set on the device matches the mains voltage, and that all subsystems are correctly wired.

3.2.2 IEC Bus Particularities

Up to 31 IEC-compatible devices can be connected to the IEC interface of the CBM 8032. All devices are connected in parallel on the bus. Each device is assigned a device address via switches or wire links. From the CBM 8032, subsystems and peripheral devices are addressed as IEC devices. The following addresses are permanently reserved:

Device Address	Device/System
0	Keyboard
1	1st cassette recorder
2	2nd cassette recorder
3	Screen
4	Printer
8	Disk drive

The interface to the analog section is factory-set to address 30 (set via switches on the rear of the interface). The MONITOR program references this address 30. For additional IEC devices, addresses 9 through 29 are available.

3.2.3 Correct Connections

Both the CBM 8032 and the interface/analog section must be connected to the mains (the latter two share a common mains connection). The cassette recorder is connected to socket J3. The cable to the DO 910 interface is plugged into socket J1. All connectors are coded so that incorrect insertion is not possible.

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4. Operating the System

4.1 Switching On

The system is switched on via the mains switches of the CBM 8032 and the interface. After a short warm-up period, the screen displays:

READY.
### COMMODORE BASIC ###
31743 bytes free

To switch from lower to upper case, use the command POKE 59486,12 (RETURN) or press both SHIFT keys simultaneously together with key 2. To switch back from upper to lower case, use POKE 59468,14 (RETURN).

4.2 Program Input

Three methods of program input are available:

4.2.1 Manual Entry

When the screen shows READY, programs or individual commands can be entered from the keyboard. Multiple commands can be entered on a single line separated by colons, and will be executed immediately upon pressing RETURN.

4.2.2 Cassette Input

Insert the cassette into the recorder, rewind to the start with REW, then press STOP on the cassette deck. Load the program with:

LOAD "Name" (RETURN)

The computer will prompt: PRESS PLAY ON TAPE #1. After pressing PLAY, the program is searched and loaded. If the desired program is at the beginning of the tape, LOAD (RETURN) suffices. Loading and starting a program at the tape start is accomplished by pressing SHIFT+RUN/STOP.

4.2.3 Disk Input

For disk input, the user is referred to the relevant disk drive manual for LOAD and file-handling commands.

4.3 The DO 910 MONITOR

4.3.1 General

The DO 910 MONITOR is a utility program by which any interface function — and thus also the functions of the analog components — can be controlled via simple keyboard entries. The MONITOR simplifies manual operation, in effect turning the DO 910 into a convenient analog computer. The MONITOR is loaded with:

LOAD "MONITOR" (RETURN)

4.3.2 Structure

After starting the MONITOR with RUN (RETURN), a main-dispatcher program awaits keyboard inputs. A valid input is interpreted and a corresponding subroutine called. Upon completion, control returns to the dispatcher. Invalid inputs are ignored.

4.3.3 MONITOR Status Display

A few seconds after starting, the MONITOR displays a status field containing:

• Four boxes labelled A, R, H, and T: A = Initial Condition, R = Compute, H = Halt, T = accelerated time constants (lit when integrators run 10× faster)
• Numbers 1–20 indicating overload in any of up to 20 modules (displayed inverted when overloaded)
• Field ABCDE KOMP. SCHALT.: comparator and switch states for up to 5 potentiometer modules
• Field D.EING. / D.AUSG.: digital input/output states (0 or 1)
• MDAC field (upper right): last set MDAC values
• DVM (KANIS): continuously displays A/D channel 15 as a digital voltmeter

4.3.4 Main Dispatcher

Valid keyboard inputs to the dispatcher:

Input	Function
A	Initial condition (Anfangsbedingung)
R	Compute (Rechnen)
H	Halt
T	Time constant control for integrators
D	Set digital outputs / read digital inputs
M	Set MDACs / read ADC
K	Query comparator states
S	Set function switches
U	Query overload states
Z	Repetitive computing

A, H, and R are executed immediately without further input. Other functions require additional information.

4.3.5 Operating Mode Control for Integrators

• A: Initial condition
• R: Compute
• H: Halt

All integrators normally connected at the patch panel take on the selected operating mode, also indicated by LEDs on the interface front panel.

4.3.6 Time Constant Control for Integrators

Time constants are individually preset at the patch panel to 1 s or 0.1 s. The MONITOR can reduce these by a factor of 10:

• T0: Retain patch-panel preset time constants
• T1: Accelerate by factor 10 (T box in status field lights up)

4.3.7 Digital Inputs/Outputs

• DE: Reads the digital inputs and displays their states in the status field behind D.EING.
• DA: Prompts for the desired states (0 or 1) for each of the 8 outputs, then sets them accordingly.

4.3.8 ADC and MDAC

• CA: Lists the currently presented voltages (in millivolts) at all 16 analog inputs.
• CD: Prompts for channel number (0–3 for MDACs) and value (four digits, no leading zero or decimal point, e.g. -1234 for −0.1234). Sets the specified MDAC.

4.3.9 Querying Comparator States

Input K triggers display of the five comparator states in the status field behind KOMP. State 1 is shown when the sum of input voltages at a comparator is positive.

4.3.10 Querying Overload States

Input U displays which modules contain at least one overloaded element by inverting the module number in the status field. Overload is not continuously queried; it reflects the state at the time of input U.

4.3.11 Setting Function Switches

Input S prompts the user to enter desired states (0 or 1) for switches A through E. After the fifth entry, the switches are set and their states shown in the status field.

4.3.12 Repetitive Computing

Input Z prompts for TAB (initial condition time) and TDR (compute time) in milliseconds. The repetitive cycle then runs indefinitely. The lower limit for TAB and TDR is approximately 20 ms. Press ESC to abort.

4.3.13 Exiting the MONITOR

ESC exits the MONITOR. If pressed while a subroutine is awaiting input, control returns to the dispatcher.

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5. Summing Amplifier Module

5.1 Patch Field Connections

A summing amplifier plug-in contains three amplifiers:

• Upper summer: two unity-gain inputs, fixed feedback.
• Middle summer: one unity-gain input, two ×10 inputs, and an accessible summing point; fixed feedback.
• Lower summer (open amplifier): four unity-gain inputs, two ×10 inputs, summing point accessible; one unity-gain input is normally used as feedback. If the amplifier is not connected in feedback, the overload indicator will trigger.

5.2 Programming

The summing amplifiers implement operations such as:

• Y1 = −(X1 + X2)
• Y2 = −(X3 + 8·X4)
• Y3 = −(X5 + 10·X6)
• Y1 = −5·X1; Y2 = −5·(X2 + X3); Y3 = −(A·X4 + X5 + 0.1·X6)

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6. Integrator Module

6.1 Patch Field Connections

Each integrator can also be operated as a summer. Each integrator’s operating mode and time constant (feedback capacitor) can be controlled individually. Two types of integrators exist: electronic switching and relay switching. Their function is identical (electronic switching has shorter mode-switching times). An unconnected (open-loop) integrator/summer can trigger the overload indicator.

6.2 Operation as Integrator

To operate as an integrator, short the sockets marked with an integral sign and select an integration capacitor. To use collective control, connect the H and S control inputs to the HT and DR busbars. The two-bit truth table for operating modes is:

Mode	HT	DR
Initial Condition (AB)	0	1
Compute (DR)	1	0
Halt (HT)	0	0

For relay-controlled integrators, state 0 = relay ground applied, state 1 = open input (open-collector driver).

6.3 Time Constant Control

Each integrator can select one of three time constants via shorting plugs at the patch field or via the interface’s collective control:

Connection (Amplifier output to…)	MONITOR control	Capacitor	Time constant at 1 MΩ input
×1	T0	1 µF	1 s
×10	T0	0.1 µF	0.1 s
×1	T1	0.1 µF	0.1 s
×10	T1	0.01 µF	0.01 s

6.4 Operation as Complementary Integrator

A complementary integrator differs only in the horizontal arrangement of the shorting plugs in the control field, swapping AB and DR modes.

6.5 Operation as Summer

When operated as a summer, the S and H control inputs are left unconnected.

6.6 Special Circuits

Several special configurations of the integrator/summer module can save computing elements, including sample-and-hold circuits and other applications described in the original document.

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7. Multiplier Module

7.1 Patch Field Connections

A multiplier plug-in contains one multiplier/divider in the upper position, one in the lower position, and two smaller summers in between (freely available). An unconnected multiplier can trigger the overload indicator.

7.2 Operation as Multiplier

A multiplier patched per the diagram computes: Y = X1 × X2, where X1 and X2 are normalized variables with magnitudes between 0 and 1.

In dimensioned notation: U_Y/10V = (U_X1/10V) × (U_X2/10V)

Input impedances: 10 MΩ (x-input), 12.5 kΩ (y-input), 36 kΩ (z-input). The z-input can be driven by a potentiometer in a suitable configuration.

7.3 Operation as Divider

Patched as a divider: Y = X2/X1. The denominator X1 must always be negative (i.e. X1 < 0) to ensure stable operation.

Dimensioned: U_Y = (U_X2/10V) / (U_X1/10V)

7.4 Operation as Square Root Extractor

Patched as a square root extractor: Y = −√X (normalized), or in dimensioned form: U_Y/10V = √(U_X/10V).

The radicand must always remain positive for stable operation. If the extractor enters instability, it does not recover automatically — a patch connection must be broken. A stabilizing circuit with a diode ensures the radicand stays positive and forces stable operation, but note that the output of the extractor then appears at the diode anode.

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8. Potentiometers

8.1 Patch Field Connections

Each potentiometer module has four hand potentiometers. Three are grounded at the low end; the fourth has a floating low end. Reference voltages +10 V (red) and −10 V (blue) are available between the potentiometers. The potentiometer wiper output is protected against short circuits and reverse voltages by a PTC resistor.

8.2 Setting

Potentiometers are passive elements whose setting depends on load. A three-position switch on the module allows the inputs of P1/P2 or P3/P4 to be switched from the patch field to +10 V for precise setting. Connecting the output to ADC channel 15 and using the MONITOR DVM display allows precise coefficient adjustment. Notes:

• P4 requires the low end to be grounded for normal use.
• After changing a potentiometer’s output load, it must be re-adjusted.
• Nonlinear components (function generators, etc.) should not be fed from a potentiometer due to variable input impedance.

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9. Comparators

9.1 Patch Field Connections

Each comparator has inputs E1 and E2 and a logic output K. The polarity of the sum of input voltages at E1 and E2 determines the state of K and the position of a downstream relay. RTR is a separate driver input for this relay.

9.2 Operation

Comparator truth table:

E1+E2	RTR input	Output K	Relay position
Positive	Open	0	0
Negative	Open	1	1
Any	0	—	0
Any	1	—	1

The relay can be driven independently via RTR by an external TTL-level logic signal, or even an analog voltage (switching point approximately +1.5 V). The logic output K can drive all DO 910 logic elements with TTL specifications. The comparator state can be queried via the interface with secondary address SA=9; each bit corresponds to one comparator (A=1, B=2, C=4, D=8, E=16).

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10. Function Switches

10.1 Patch Field Connections

Each potentiometer module contains one function switch. The HAND socket is the logic output. The RTR input is a relay driver input (identical arrangement to the comparator).

10.2 Operation

Switches are set via the interface with secondary address SA=6 and data 0–31:

Bit	1	2	4	8	16
Switch	A	B	C	D	E

Setting a bit to 1 places the corresponding switch in position 1; the HAND output then provides a logic 1.

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11. Limiters

11.1 General

Each potentiometer module contains an adjustable limiter for clamping the output voltage of an amplifier. Adjustment potentiometers for upper and lower limits are at the top and bottom edges of the connection field.

11.2 Operation as Limiter

Connect the limiter’s socket A to the output of the amplifier to be limited, and its SP socket to the amplifier’s summing point SP. The limiter can only be used with amplifiers whose summing point is accessible on the patch field. Both clamp levels can be set in the same half-plane (e.g. both positive), as long as the upper limit is set above the lower limit.

11.3 Simulation of Special Nonlinearities

Limiters can simulate a range of nonlinear characteristics, including:

• Absolute value function: Using a limiter with an appropriately patched circuit
• Signum function: Circuit and characteristic described in the original document
• Dead zone: Width 2z determined by control variable z; accurate with antiparallel diodes (without them, error ≈ 0.5 V)
• Rectangle hysteresis: Two-level hysteresis characteristic
• Three-point hysteresis: Symmetric three-level hysteresis; special cases include both clamps in the same half-plane

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12. Variable Diode Function Generator

12.1 General

Each function generator plug-in contains two adjustable function generators with equidistant breakpoints. The upper generator has 2×5 = 10 breakpoints; the lower has 2×4 = 8 breakpoints. An arbitrary function can be approximated by a polygon in all four quadrants.

A fixed function generator is also present for simulating special nonlinearities such as signum function, dead zone, etc.

12.2 Structure

Slope potentiometers on the front panel of the module set the slopes between breakpoints. The lower function generator is equipped with a relay for parallel operation. Its output amplifier has an additional unity-gain input enabling the addition of a variable: Y2 = f(x2) + Z.

12.3 Function Generator Adjustment

12.3.1 Adjustment Using an Oscilloscope

Set up an integrator-based ramp generator and run the DO 910 in repetitive mode with TAB and TDR ≈ 20 ms. The oscilloscope will display a stationary image of the currently set function.

Procedure:

1. Set f(x=0) with the Y0 potentiometer.
2. Adjust the initial slope (Ylin potentiometer) so that f(x1) has the correct value at x=1 V.
3. Adjust slope potentiometer 1 to achieve f(x3) at x=3 V.
4. Repeat for remaining breakpoints.
5. Then set the function for negative x values starting from x=−1 V.
6. Verify the full set function and correct if necessary.

12.3.2 Adjustment Using the Digital Voltmeter

Most accurate but most time-consuming method. Set up the measurement circuit (the function generator must be fed from a low-impedance source, hence a downstream amplifier is used). The DVM is realized using MONITOR channel 15. Set breakpoints one at a time, adjusting each slope potentiometer for the corresponding breakpoint value. The function may need a second-pass correction.

12.3.3 Adjustment Using an x-y Plotter

A compromise method. Draw the desired normalized function on x-y paper. Build the measurement circuit and set breakpoints while observing the approximation quality on the plotter in real time.

12.4 Paralleling Function Generators

To double the number of breakpoints, connect socket P to the relay ground below it. This internally parallels the lower function generator network with the upper one, creating a function generator with equidistant breakpoints from −9 V to +9 V. The lower function generator’s output amplifier and Y0 potentiometer are then freed for other tasks. Slope adjustment proceeds in alternating sequence: upper, lower, upper, etc.

12.5 Fixed Function Generator

The fixed function generator in the upper part of the module has three connections: E1, E2 (both input/output, direction arbitrary) and S (control input). Applications include:

• Signum function: Control signal z determines the amplitude. Antiparallel diodes in the feedback correct a ~0.5 V error.
• Dead zone: Width 2z with antiparallel diodes; without them, an error of ~0.5 V in the half-width.
• Three-point characteristic: Clamps set via limiter adjustment potentiometers; breadth 2z per control variable; special cases include clamps in the same half-plane.

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13. Logic Components

13.1 General

Logic modules can be placed in any of the 20 slots alongside analog elements. Available plug-in types:

• Clock generator module with two 4-bit counters
• Flip-flop module with three flip-flops and one monoflop
• Gate module with five AND/NAND gates

Logic components should be placed in the leftmost positions (starting at position 1) to minimize interference with analog elements. The clock generator module (which carries a shielding plate) should be placed rightmost within the logic group. All logic components are TTL with:

• Logic 0: 0 V to +0.8 V
• Logic 1: +2.4 V to +5 V

All inputs and outputs are protected against patch-field voltages. A special output stage can drive TTL signals but also directly control relays. Each logic output can drive 10 logic inputs or 2 relays. Wired-AND and wired-OR connections between outputs are permissible.

13.2 Clock Generator Module

The clock generator consists of a 10 kHz oscillator whose output is divided by 10 in successive decades down to 1 Hz. Outputs are labelled 0 through 3 (as exponents of 10):

• Normal: 1 Hz, 10 Hz, 100 Hz, 1 kHz
• With ×10 interface acceleration: 10 Hz, 100 Hz, 1 kHz, 10 kHz

Clock pulses have a duration of 10 µs. Operating modes are controlled via R and H inputs in the lower control field:

H	R	Mode
1	0	Initial condition (reset)
1	1	Initial condition
0	1	Clock generator runs
0	0	Clock generator halted (state preserved)

Normally, R and H are connected to the DR and HT busbars, so the clock follows the integrator operating modes.

13.2.1 4-Bit Counter

The 4-bit counter is a binary up-counter. Connections:

• T: Clock input — increments on negative (falling) edge when R=0
• RS: Reset — a positive (rising) edge resets to 0 and blocks for ~3 µs
• R: Control — high at T reset simultaneously; with normal connection, counter follows integrator modes. In HT mode, counter continues if T pulses are present.
• 1, 2, 4, 8: Outputs for respective bit weights; LED indicators light when output = 1

The counter counts up to 15 pulses; the 16th resets to 0.

Applications:

• Extending beyond 4 bits: Connect the 8-output of one counter to the T-input of the next; two counters count up to 255.
• Decimal counter: Parallel the outputs corresponding to the desired count; the wired-AND produces a pulse at that count.
• Auto-reset: Connect the Z output (from the AND combination) back to RS; the counter resets automatically on reaching the preset value and begins again.

13.3 Flip-Flop Module

The flip-flop module contains three RS flip-flops and one monoflop. LED indicators show the state of each flip-flop.

13.3.1 Flip-Flops

Each flip-flop has the following inputs:

• S: Set input — logic 0 sets flip-flop to F=1 (LED on)
• R: Reset input — logic 0 resets flip-flop to F=0 (LED off)
• T: Clock input — state changes on every negative (falling) edge
• F, F̄: True and inverted outputs
• R (lower control field): Mode control

Operating mode truth table: logic 0 at R resets all flip-flops to F=0; logic 1 allows normal operation. Normally, the S input of the lower control field is connected to the RS busbar, so all three flip-flops are reset during Initial Condition and operate normally during Compute and Halt.

Note: The RS socket in the flip-flop module is not identical to the RS socket in the clock generator module.

13.3.2 Monoflop

Inputs:

• T: Clock input — every positive (rising) edge sets output M = 1 for an adjustable time
• M: Output
• C: Connection for an external capacitor to extend the pulse duration

Pulse width range without external capacitor: ~10 µs to ~1 ms. With external capacitors:

Capacitor	Maximum pulse width
10 nF	2 ms
100 nF	10 ms
1 µF	100 ms
10 µF	1 s

Recovery time is approximately 0.5 µs/nF. The monoflop does not operate when the R control input has state 0.

13.4 Gate Module

Each gate module contains five AND/NAND gates:

A1	A2	B (AND)	B̄ (NAND)
0	0	0	1
0	1	0	1
1	0	0	1
1	1	1	0

The number of inputs can be extended by paralleling gate outputs (wired-AND), up to 4-input AND gates by paralleling two gates.

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14. Dead-Time Element

14.1 General

Dead-time elements simulate transport delays and the transfer function e^(−T·s). The DO 910 provides a dead-time plug-in for this purpose. The element can be placed in any slot but should be positioned in the leftmost slots (like logic components) to avoid internal clock interference with analog elements.

The dead time is generated by digitizing the input voltage U1 through an 8-bit A/D converter, feeding it into a shift register (100 words × 8 bits), and after 100 shift pulses, the signal reappears at the output of the shift register and is reconverted to an analog voltage via the D/A converter. The frequency of the shift clock determines the dead time.

14.2 Patch Field Connections

The dead-time plug-in also contains two freely available diodes for special nonlinear applications or in conjunction with the fixed function generator.

14.3 Structure

A clock signal applied to the TAKT input serves as the converter and shift clock. The clock can be derived from any logic module or from the built-in voltage-to-frequency (V/F) converter. The V/F converter output frequency is linearly proportional to the voltage at the Uf socket. It can be multiplied by 10 using the ×10 sockets, and by a further factor of 10 via the interface secondary address SA=4 (giving a factor of 100 total). The A/D converter has a preamplifier with inputs of weight 1 and 10. RING sockets connect the shift register output back to its input (ring shift register mode).

14.4 V/F Converter Range

The relationship between input voltage Uf and output frequency is linear: f = a × Uf (Uf must be negative for converter operation):

Bridges (×1 or ×10)	For Uf = −0.1 V to −10 V	Frequency f	Dead time
×1	—	10 Hz … 1 kHz	10 s … 100 ms
×10	—	100 Hz … 10 kHz	1 s … 10 ms

With ×10 interface acceleration, the shortest achievable dead time is 1 ms. The relationship between Uf and dead time Tt is hyperbolic: Tt = 100 / (a × Uf).

14.5 Operating Mode Control

Control via R and H inputs. With the normal connection to DR and HT busbars:

• DR: V/F converter operates per the settings in 14.4.
• HT: Converter halted; current state of the shift register is frozen.
• AB: A special frequency generator outputs a 100 kHz signal for 1 ms as shift clock, simultaneously loading zeros into the shift register input. Thus the shift register is cleared in 1 ms. This clearing occurs regardless of the clock source (V/F or external).

14.6 Operation as Ring Shift Register

Bridging the RING sockets disconnects the shift register input from the A/D converter and connects it to the shift register output. The current shift register contents are cyclically output according to the shift clock. The dead-time element can thus also be used as a function generator.

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Appendix: IEC Transfers in BASIC

(Appendix to the DO 910 Operator’s Manual)

1. General

This appendix describes how the DO 910 user can program IEC/IEEE bus transfers independently. Key terms:

• File (logische Datei): Any device or subsystem that can send or receive data is treated as a logical file with a logical file number (LF).
• Device address (GA): Hardware-set, range 0–31.
• Secondary address (SA): Device-specific, selects function within the device.

The OPEN command associates a logical file number with a device address and secondary address:

OPEN LF, GA, SA, "NAME"

Data output uses PRINT#LF; data input uses GET#LF or INPUT#LF. The GET#LF command is preferred for IEC transfers, as INPUT#LF can cause issues with the CBM 8032 operating system. Transfers conclude with CLOSE LF.

2. Write Transfer

OPEN LF, GA, SA
PRINT#LF, CHR$(D)
CLOSE LF

CHR$(D) generates an ASCII character with value D.

3. Read Transfer

OPEN LF, GA, SA
GET#LF, R$
IF R$="" THEN R$=CHR$(0)
R=ASC(R$)
CLOSE LF

The null-check (IF R$="" THEN R$=CHR$(0)) is necessary because ASC() fails on the null character.

4. Application to the DO 910

The interface factory device address is GA=30 (adjustable via switches on the interface rear panel). The MONITOR program references address 30.

Interface switch meanings:

• A5–A1: Device address bits
• TON: Talker Only (device can only send)
• LON: Listener Only (device can only receive)
• TL: Talker & Listener (device can do both)
• RTL: Remote Talker/Listener (can be remotely controlled)
• IEC/CBM: 0 = CBM as controller; 1 = 100% IEC-standard interface

4.2 DO 910 Write Functions

Function	SA	Data
Set digital outputs	0	0–255
Set multiplexer and start ADC	1	0–15
Start ADC	2	—
SRQ enable/disable	3	0=enable, 1=disable
Set T/10	4	0=normal, 1=T/10
Set operating modes	5	0=HALT, 1=COMPUTE, 2=INITIAL CONDITION
Set function switches ABCDE	6	0–31
MDAC 0: set 8 MSB	7	0–255
MDAC 0: set 4 LSB	8	0–15
MDAC 1: set 8 MSB	9	0–255
MDAC 1: set 4 LSB	10	0–15
MDAC 2: set 8 MSB	11	0–255
MDAC 2: set 4 LSB	12	0–15
MDAC 3: set 8 MSB	13	0–255
MDAC 3: set 4 LSB	14	0–15

4.3 DO 910 Read Functions

Function	SA	Data
Read digital inputs	0	0–255
Read digital outputs	1	0–255
Read ADC 8 MSB	2	0–255
Read ADC 4 LSB and multiplexer channel	3	0–15/16–255
Read ADC 8 MSB, increment multiplexer, start ADC	4	0–255
Read ADC 8 MSB and start ADC	5	0–255
Read overload register 1	6	0–255
Read overload register 2	7	0–255
Read overload register 3	8	0–255
Read comparator states (incl. overload summary on bit 128)	9	0–63, 0–31

5. Setting Digital Outputs

OPEN 1, 30, 0
PRINT#1, CHR$(D)
CLOSE 1

Bit assignment: digital outputs 0–7 correspond to data bits 1, 2, 4, 8, 16, 32, 64, 128.

Example — set outputs 1 and 3: D = 2 + 8 = 10.

6. Reading Digital Inputs

OPEN 1, 30, 0
GET#1, D$: IF D$="" THEN D$=CHR$(0)
D=ASC(D$)
CLOSE 1

Same bit assignment as outputs. Open (unconnected) inputs read as 1.

7. Working with the A/D Converter

The ADC has 12-bit resolution, requiring two IEC transfers to convey the full word (8 MSB + 4 LSB). For higher speed, reading only the 8 MSB provides ~80 mV resolution. A programming example:

10 OPEN 1,30,1: OPEN 2,30,2: OPEN 3,30,3
20 PRINT#1, CHR$(5)
30 GET#2, M$: GET#3, L$
40 IF M$="" THEN M$=CHR$(0)
50 IF L$="" THEN L$=CHR$(0)
60 W=INT((16*ASC(M$)+(ASC(L$) AND 15))/2.048)
70 IF ASC(M$)>127 THEN W=-20000+W
80 CLOSE 1: CLOSE 2: CLOSE 3

Lines 10–80: Opens multiplexer-set/ADC-start, 8 MSB read, and 4 LSB/multiplexer read files; sets multiplexer and starts ADC; reads and converts the 12-bit result to millivolts (0–10000 for 0–10 V, −10000–−1 for negative voltages after line 70 correction).

For cyclic ADC reading at higher speed, use SA=4 which reads 8 MSB, increments the multiplexer, and restarts the ADC in a single transfer.

8. Working with the Multiplying D/A Converters (MDACs)

The four MDACs have 12-bit resolution, also requiring two IEC transfers. An MDAC output is negative when set to a positive digital value, due to the following coding:

Digital code	Analog coefficient
000000000000	0
011111111111	−0.4999…
100000000000	+1.0000

Example — set MDAC 2 to coefficient +0.5:

OPEN 1, 30, 11
OPEN 2, 30, 12
K=0.5
PRINT#1, CHR$((-128*K) AND 255)
PRINT#2, CHR$((-2048*K) AND 15)
CLOSE 1: CLOSE 2

9. Setting Function Switches

OPEN 1, 30, 6
PRINT#1, CHR$(5)
CLOSE 1

Bit assignment: switches A–E correspond to bits 1, 2, 4, 8, 16. Setting bit 0 places switch in position 0; setting bit 1 places switch in position 1. Example: CHR$(5) = bit 0 (A) + bit 2 (C) = switches A and C in position 1, others in position 0.

10. Reading Comparator States

OPEN 6, 30, 9
GET#6, K$: IF K$="" THEN K$=CHR$(0)
K=ASC(K$)
CLOSE 6

Comparators A–E correspond to bits 1, 2, 4, 8, 16. Bit 128 carries the overload summary signal. A bit value of 1 indicates the comparator has a positive input sum.

11. Reading Overload States

Up to 20 modules can generate overload signals. These are read via three secondary addresses:

SA	Modules
6	1–8
7	9–16
8	17–20

The lowest-addressed module’s overload appears on the LSB. To avoid reading all three registers, the overload summary signal is also readable on bit 128 when querying comparator states with SA=9.