Reference / Paper · 2021

Understanding Operational Amplifier Specifications

A Texas Instruments application report (SLOA011B, revised July 2021) by Jim Karki that explains how to interpret operational amplifier data sheet specifications. The document covers the ideal op amp model, non-inverting and inverting amplifier topologies, a simplified internal circuit diagram, and a detailed treatment of seventeen key parameters including input offset voltage, bias current, common-mode rejection ratio, slew rate, gain-bandwidth product, noise, THD+N, and settling time. It is intended to help engineers select op amps by understanding what published specifications mean and how TI defines and tests each parameter.

Manufacturer: Texas Instruments
Author: Jim Karki
Year: 2021
Type: Reference / Paper
Language: English
Learning track: general theory
Pages: 25
Credit: Texas Instruments, Inc. Application Report SLOA011B, originally January 2018, revised July 2021. Copyright 2021-2022 Texas Instruments Incorporated.

Texas Instruments
operational amplifiers
op-amp specifications
analog circuit theory
amplifier design

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www.ti.com Table of Contents Application Report Understanding Operational Amplifier Specifications Jim Karki ABSTRACT Selecting the right operational amplifier for a specific application requires you to have your design goals clearly in mind along with a firm understanding of what the published specifications mean. This paper addresses the issue of understanding data sheet specifications. This paper begins with background information. First, introductory topics on the basic principles of amplifiers are presented, including the ideal op amp model. As an example, two simple amplifier circuits are analyzed using the ideal model. Second, a simplified circuit of an operational amplifier is discussed to show how parameters arise that limit the ideal functioning of the operational amplifier. The paper then focuses on op amp specifications. Texas Instruments’ data book, Amplifiers, Comparators, and Special Functions, is the basis for the discussion on op amp specifications. Information is presented about how Texas Instruments defines and tests operational amplifier parameters. Table of Contents 1 Introduction.............................................................................................................................................................................3 1.1 Amplifier Basics..................................................................................................................................................................3 1.2 Ideal Op Amp Model.......................................................................................................................................................... 3 2 Non-Inverting Amplifier..........................................................................................................................................................5 2.1 Closed Loop Concepts and Simplifications........................................................................................................................6 3 Inverting Amplifier.................................................................................................................................................................. 6 3.1 Closed Loop Concepts and Simplifications........................................................................................................................7 4 Simplified Op Amp Circuit Diagram......................................................................................................................................8 4.1 Input Stage.........................................................................................................................................................................9 4.2 Second Stage.....................................................................................................................................................................9 4.3 Output Stage...................................................................................................................................................................... 9 5 Op Amp Specifications...........................................................................................................................................................9 5.1 Absolute Maximum Ratings and Recommended Operating Condition.............................................................................. 9 5.2 Input Offset Voltage..........................................................................................................................................................10 5.3 Input Current.....................................................................................................................................................................11 5.4 Input Common Mode Voltage Range............................................................................................................................... 11 5.5 Differential Input Voltage Range.......................................................................................................................................13 5.6 Maximum Output Voltage Swing...................................................................................................................................... 14 5.7 Large Signal Differential Voltage Amplification.................................................................................................................14 5.8 Input Parasitic Elements.................................................................................................................................................. 15 5.9 Output Impedance............................................................................................................................................................16 5.10 Common-Mode Rejection Ratio..................................................................................................................................... 16 5.11 Supply Voltage Rejection Ratio...................................................................................................................................... 16 5.12 Supply Current............................................................................................................................................................... 17 5.13 Slew Rate at Unity Gain................................................................................................................................................. 17 5.14 Equivalent Input Noise................................................................................................................................................... 17 5.15 Total Harmonic Distortion Plus Noise.............................................................................................................................18 5.16 Unity-Gain Bandwidth and Phase Margin...................................................................................................................... 19 5.17 Settling Time.................................................................................................................................................................. 21 6 References............................................................................................................................................................................ 22 7 Glossary................................................................................................................................................................................ 22 8 Revision History................................................................................................................................................................... 24 SLOA011B – JANUARY 2018 – REVISED JULY 2021 Submit Document Feedback Understanding Operational Amplifier Specifications Copyright © 2021 Texas Instruments Incorporated 1 Table of Contents www.ti.com List of Figures Figure 1-1. Thevenin Model of Amplifier with Source Load......................................................................................................... 3 Figure 1-2. Standard Op Amp Notation....................................................................................................................................... 4 Figure 1-3. Ideal Op Amp Model..................................................................................................................................................4 Figure 2-1. Non-Inverting Amplifier..............................................................................................................................................5 Figure 3-1. Inverting Amplifier......................................................................................................................................................7 Figure 4-1. Simplified Op Amp Circuit Diagram...........................................................................................................................8 Figure 5-1. VIO.......................................................................................................................................................................... 10 Figure 5-2. Positive Common-Mode Voltage Input Limit............................................................................................................11 Figure 5-3. Negative Common-Mode Input Limit.......................................................................................................................12 Figure 5-4. Differential-Mode Voltage Input Limit.......................................................................................................................13 Figure 5-5. VOM±...................................................................................................................................................................... 14 Figure 5-6. Input Parasitic Elements..........................................................................................................................................15 Figure 5-7. Effect Output Impedance.........................................................................................................................................16 Figure 5-8. Slew Rate................................................................................................................................................................ 17 Figure 5-9. Typical Op Amp Input Noise Spectrum................................................................................................................... 18 Figure 5-10. Output Spectrum with THD + N = 1%................................................................................................................... 19 Figure 5-11. Typical Large-Signal Differential Voltage Amplification and Phase Shift vs. Frequency........................................20 Figure 5-12. Easier to Read Graph of Voltage Amplification and Phase Shift vs. Frequency................................................... 21 Figure 5-13. Settling Time..........................................................................................................................................................21 2 Understanding Operational Amplifier Specifications Copyright © 2021 Texas Instruments Incorporated SLOA011B – JANUARY 2018 – REVISED JULY 2021 Submit Document Feedback www.ti.com Introduction 1 Introduction The term operational amplifier, abbreviated op amp, was coined in the 1940s to refer to a special kind of amplifier that, by proper selection of external components, can be configured to perform a variety of mathematical operations. Early op amps were made from vacuum tubes consuming lots of space and energy. Later op amps were made smaller by implementing them with discrete transistors. Today, op amps are monolithic integrated circuits, highly efficient and cost effective. 1.1 Amplifier Basics Before jumping into op amps, lets take a minute to review some amplifier fundamentals. An amplifier has an input port and an output port. In a linear amplifier, output signal = A × input signal, where A is the amplification factor or gain. Depending on the nature of input and output signals, we can have four types of amplifier gain: • Voltage (voltage out/voltage in) • Current (current out/current in) • Transresistance (voltage out/current in) • Transconductance (current out/voltage in) Since most op amps are voltage amplifiers, we will limit our discussion to voltage amplifiers. Thevenin’s theorem can be used to derive a model of an amplifier, reducing it to the appropriate voltage sources and series resistances. The input port plays a passive role, producing no voltage of its own, and its Thevenin equivalent is a resistive element, Ri. The output port can be modeled by a dependent voltage source, AVi, with output resistance, Ro. To complete a simple amplifier circuit, we will include an input source and impedance, Vs and Rs, and output load, RL. Figure 1-1 shows the Thevenin equivalent of a simple amplifier circuit. RS RO ± Source RI + AVi Output Port VI Input Port + + VS + VL RL ± Amplifier Load Figure 1-1. Thevenin Model of Amplifier with Source Load It can be seen that we have voltage divider circuits at both the input port and the output port of the amplifier. This requires us to re-calculate whenever a different source and/or load is used and complicates circuit calculations. 1.2 Ideal Op Amp Model The Thevenin amplifier model shown in Figure 1-1 is redrawn in Figure 1-2 showing standard op amp notation. An op amp is a differential to single-ended amplifier. It amplifies the voltage difference, Vd = Vp - Vn, on the input port and produces a voltage, Vo, on the output port that is referenced to ground. SLOA011B – JANUARY 2018 – REVISED JULY 2021 Submit Document Feedback Understanding Operational Amplifier Specifications Copyright © 2021 Texas Instruments Incorporated 3 Introduction www.ti.com IN + ± VN ± VD RI + AVd RO + VO ± + + IP VP ± Figure 1-2. Standard Op Amp Notation We still have the loading effects at the input and output ports as noted above. The ideal op amp model was derived to simplify circuit calculations and is commonly used by engineers in first-order approximation calculations. The ideal model makes three simplifying assumptions: • Gain is infinite a=∞ • (1) Input resistance is infinite Ri = ∞ • (2) Output resistance is zero Ro = 0 (3) Applying these assumptions to Figure 1-2 results in the ideal op amp model shown in Figure 1-3. + ± VN ± VD + AVd + VO ± + + VP ± Figure 1-3. Ideal Op Amp Model Other simplifications can be derived using the ideal op amp model: → In = Ip = 0 (4) Because Ri = ∞, we assume In = Ip = 0. There is no loading effect at the input. → Vo = a Vd 4 (5) Understanding Operational Amplifier Specifications Copyright © 2021 Texas Instruments Incorporated SLOA011B – JANUARY 2018 – REVISED JULY 2021 Submit Document Feedback www.ti.com Non-Inverting Amplifier Because Ro = 0 there is no loading effect at the output. → Vd = 0 (6) If the op amp is in linear operation, V0 must be a finite voltage. By definition Vo = Vd × a. Rearranging, Vd = Vo / a . Since a = ∞, Vd = Vo / ∞ = 0. This is the basis of the virtual short concept. → Common mode gain = 0 (7) The ideal voltage source driving the output port depends only on the voltage difference across its input port. It rejects any voltage common to Vn and Vp. → Bandwidth = ∞ (8) → Slew Rate = ∞ (9) No frequency dependencies are assumed. → Drift = 0 (10) There are no changes in performance over time, temperature, humidity, power supply variations, etc. 2 Non-Inverting Amplifier An ideal op amp by itself is not a very useful device since any finite input signal would result in infinite output. By connecting external components around the ideal op amp, we can construct useful amplifier circuits. Figure 2-1 shows a basic op amp circuit, the non-inverting amplifier. The triangular gain block symbol is used to represent an ideal op amp. The input terminal marked with a + (Vp) is called the non-inverting input; – (Vn) marks the inverting input. + VP + VI VN ± + I R2 Vo ± R1 Feedback Network Figure 2-1. Non-Inverting Amplifier To understand this circuit we must derive a relationship between the input voltage, Vi, and the output voltage, Vo. Remembering that there is no loading at the input, Vp = VI (11) The voltage at Vn is derived from Vo via the resistor network, R1 and R2, so that, VN VO R1 R1 R2 VO b (12) where, b R1 R1 R2 (13) The parameter b is called the feedback factor because it represents the portion of the output that is fed back to the input. Recalling the ideal model, SLOA011B – JANUARY 2018 – REVISED JULY 2021 Submit Document Feedback Understanding Operational Amplifier Specifications Copyright © 2021 Texas Instruments Incorporated 5 Non-Inverting Amplifier www.ti.com Vo = aVσ = a(Vp - Vn) (14) Substituting, Vo = a(Vi - bVo) (15) and collecting terms yield, A § · § 1· ¨ 1 ¸ ¸ ¨b¸ ¨ © ¹ ¨1 1 ¸ ¨ ¸ ab ¹ © VO VI (16) This result shows that the op amp circuit of Figure 2-1 is itself an amplifier with gain A. Since the polarity of Vi and VO are the same, it is referred to as a non-inverting amplifier. A is called the close loop gain of the op amp circuit, whereas a is the open loop gain. The product ab is called the loop gain. This is the gain a signal would see starting at the inverting input and traveling in a clockwise loop through the op amp and the feedback network. 2.1 Closed Loop Concepts and Simplifications Substituting a = ∞ Equation 1 into Equation 16 results in, A 1 b R2 R1 1 (17) Recall that in equation Equation 6 we state that Vd, the voltage difference between Vn and Vp, is equal to zero and therefore, Vn = Vp. Still they are not shorted together. Rather there is said to be a virtual short between Vn and Vp. The concept of the virtual short further simplifies analysis of the non-inverting op amp circuit in Figure 2-1. Using the virtual short concept, we can say that, Vn= Vp = Vi (18) Realizing that finding Vn is now the same resistor divider problem solved in Equation 12 and substituting Equation 18 into it, we get, VI VO R1 R1 R2 VO b (19) Rearranging and solving for A, we get, A § 1· ¨b¸ © ¹ 1 § R2 · ¨ R1 ¸ © ¹ (20) The same result is derived in Equation 17. Using the virtual short concept reduced solving the non-inverting amplifier, shown in Figure 2-1, to solving a resistor divider network. 3 Inverting Amplifier Figure 3-1 shows another useful basic op amp circuit, the inverting amplifier. The triangular gain block symbol is again used to represent an ideal op amp. The input terminal, + (Vp), is called the non-inverting input, whereas – (Vn) marks the inverting input. It is similar to the non-inverting circuit shown in Figure 2-1 except that now the signal is applied to the inverting terminal via R1 and the non-inverting terminal is grounded. 6 Understanding Operational Amplifier Specifications Copyright © 2021 Texas Instruments Incorporated SLOA011B – JANUARY 2018 – REVISED JULY 2021 Submit Document Feedback www.ti.com Inverting Amplifier + VP R1 VN ± + VI + R2 VO ± I Figure 3-1. Inverting Amplifier To understand this circuit, we must derive a relationship between the input voltage, Vi and the output voltage, Vo. Since Vp is tied to ground, Vp = 0 (21) Remembering that there is no current into the input, the voltage at Vn can be found using superposition. First let Vo = 0, VN § R2 · VI ¨ ¸ © R1 R2 ¹ (22) Next let Vi = 0, VN § R1 · VO ¨ ¸ © R1 R2 ¹ (23) Combining VN § § R2 · R1 · VO ¨ ¸ VI ¨ ¸ R1 R2 © ¹ © R1 R2 ¹ (24) Remembering equation Equation 14, Vo = aVd = a(Vp - Vn), substituting and rearranging, A VO 1 VI § · 1 ¸ § 1· ¨ ¸ ¨ b¸ ¨ © ¹¨1 1 ¸ ¨ ¸ ab ¹ © (25) where b R1 R1 R2 (26) Again we have an amplifier circuit. Because b ≤ 1, the closed loop gain, A, is negative, and the polarity of Vo will be opposite to Vi. Therefore, this is an inverting amplifier. 3.1 Closed Loop Concepts and Simplifications Substituting a = ∞ Equation 1 into Equation 24 results in A 1 1 b R2 R1 (27) Recall that in equation Equation 6 we stated that Vd, the voltage difference between Vn and Vp, was equal to zero so that Vn = Vp. Still they are not shorted together. Rather there is said to be a virtual short between Vn and Vp. The concept of the virtual short further simplifies analysis of the inverting op amp circuit in Figure 3-1. SLOA011B – JANUARY 2018 – REVISED JULY 2021 Submit Document Feedback Understanding Operational Amplifier Specifications Copyright © 2021 Texas Instruments Incorporated 7 Simplified Op Amp Circuit Diagram www.ti.com Using the virtual short concept, we can say that Vn = Vp = 0 (28) In this configuration, the inverting input is a virtual ground. We can write the node equation at the inverting input as VN VI VN R1 VO 0 (29) R1 Since Vn = 0, rearranging, and solving for A we get A 1 1 b R2 R1 (30) The same result is derived more easily than in (Equation 24. Using the virtual short (or virtual ground) concept reduced solving the inverting amplifier, shown in Figure 3-1, to solving a single node equation. 4 Simplified Op Amp Circuit Diagram Real op amps are not ideal. They have limitations. To understand and discuss the origins of these limitations, see the simplified op amp circuit diagram shown in Figure 4-1. VCC IO Q6 D1 Q1 VN IN Q2 CC VO D2 Q7 IC1 IOUT (SOURCING) IC2 IOUT (SINKING) VP Q5 IC1 IP IOUT1 Q4 IC1 Q3 -VEE INPUT STAGE SECOND STAGE OUTPUT STAGE Figure 4-1. Simplified Op Amp Circuit Diagram Although simplified, this circuit contains the three basic elements normally found in op amps: • Input stage • Second stage • Output stage The function of the input stage is to amplify the input difference, Vp - Vn, and convert it to a single-ended signal. The second stage further amplifies the signal and provides frequency compensation. The output stage provides output drive capability. 8 Understanding Operational Amplifier Specifications Copyright © 2021 Texas Instruments Incorporated SLOA011B – JANUARY 2018 – REVISED JULY 2021 Submit Document Feedback www.ti.com Simplified Op Amp Circuit Diagram 4.1 Input Stage Symmetry of the input stage is key to its operation. Each transistor pair, Q1-Q2 and Q3-Q4, is matched as closely as possible. Q3 is diode connected. This forces the collector current in Q3 to equal IC1. The base-emitter junctions of Q3 and Q4 are in parallel so they both see the same VBE. Because Q4 is matched to Q3, its collector current is also equal to IC1. This circuit is called a current mirror. Current source 2IE is divided between Q1 and Q2. This division depends on the input voltages, Vp and Vn. When Vp is more positive than Vn, Q1 carries more current than Q2, and IC1 is larger than IC2. The current mirror action of Q3-Q4 causes IOUT1 to flow into the collector-collector junction of Q2-Q4. When Vn is more positive than Vp, Q2 carries more current than Q1 and IC2 is larger than IC1. The current mirror action of Q3-Q4 causes IOUT1 to flow out of the collector-collector junction of Q2-Q4. IOUT1 is the single-ended signal out of the first stage and is proportional to the differential input, Vp - Vn. IOUT1 = gm1(Vp - Vn). The term gm1 is called the transconductance of the input stage. The input stage is a transconductance amplifier. 4.2 Second Stage The second stage converts IOUT1 into a voltage and provides frequency compensation. If IOUT1 flows into the collectorcollector junction of Q2-Q4, the second stage output voltage is driven positive. If IOUT1 flows out of the collector-collector junction of Q2-Q4, the second stage output voltage is driven negative. The second stage is a transresistance amplifier. The capacitor, Cc, in the second stage provides internal frequency compensation. It causes the gain to role off as the frequency increases. Without Cc, external compensation is required to prevent the op amp from oscillating in most applications. 4.3 Output Stage The output stage is a typical class AB, push-pull amplifier. The emitter follower configuration of Q6 and Q7 provides current drive for the output load, with unity voltage gain. The output stage is a current amplifier. 5 Op Amp Specifications If you have experimented with op amp circuits at moderate gain and frequency, you probably have noted very good agreement between actual performance and ideal performance. As gain and/or frequency are increased, however, certain op amp limitations come into play that effect circuit performance. In theory, with proper understanding of the internal structures and processes used to fabricate an op amp, we could calculate these effects. Thankfully this is not necessary, as manufacturers provide this information in data sheets. Proper interpretation of data sheet specifications is required when selecting an op amp for an application. This discussion of op amp parameters is based on Texas Instruments’ data sheets. The following definitions (except as noted) are from the "Operational Amplifier Glossary" found in Texas Instruments’ data book, Amplifiers, Comparators, and Special Functions, pg. 1-37 to pg. 1-40 and pg. 5-37 to pg. 5-40. It defines most of the parameters found in the data sheets. 5.1 Absolute Maximum Ratings and Recommended Operating Condition The following typical parameters are listed in the absolute maximum ratings and the recommended operating conditions for TI op amps. The op amp will perform more closely to the typical values for parameters if operated under the recommended conditions. Stresses beyond the maximums listed will cause unpredictable behavior and may cause permanent damage. • Absolute Maximums – Supply Voltage – Differential input voltage – Input voltage range – Input current SLOA011B – JANUARY 2018 – REVISED JULY 2021 Submit Document Feedback Understanding Operational Amplifier Specifications Copyright © 2021 Texas Instruments Incorporated 9 Op Amp Specifications • www.ti.com – Output current – Total current into VDD+ – Total current out of VDD– Duration of short-circuit current (at or below 25°C) – Continuous total power dissipation – Operating free-air temperature – Storage temperature – Lead temperature Recommended Operating Conditions – Supply Voltage – Input voltage range – Common-mode input voltage – Operating free-air temperature 5.2 Input Offset Voltage Input offset voltage, VIO, is defined as "the DC voltage that must be applied between the input terminals to force the quiescent DC output voltage to zero or some other level, if specified". If the input stage was perfectly symmetrical and the transistors were perfectly matched, VIO = 0. Because of process variations, geometry and doping are never exact to the last detail. All op amps require a small voltage between their inverting and non-inverting inputs to balance the mismatches. VIO is normally depicted as a voltage source driving the non-inverting input, as shown in Figure 5-1. TI data sheets show two other parameters related to VIO; the average temperature coefficient of the input offset voltage and the input offset voltage long-term drift. The average temperature coefficient of input offset voltage, αVIO, specifies the expected input offset drift over temperature. Its units are uV/°C. VIO is measured at the temperature extremes of the part, and αVIO is computed as ΔVIO/Δ°C. Normal aging in semiconductors causes changes in the characteristics of devices. The input offset voltage long-term drift specifies how VIO is expected to change with time. Its units are mV/month. VCC 2IE Q1 Q2 VN + r1 VP VIO IOUT1 Q4 + VOUT = 0 ± Q3 -VEE Figure 5-1. VIO Input offset voltage is of concern anytime DC precision is required. Several methods are used to null its effects. 10 Understanding Operational Amplifier Specifications Copyright © 2021 Texas Instruments Incorporated SLOA011B – JANUARY 2018 – REVISED JULY 2021 Submit Document Feedback www.ti.com Op Amp Specifications 5.3 Input Current Referring to Figure 4-1, we can see that a certain amount of bias current is required at each input. The input bias current, IIB, is computed as the average of the two inputs, IIB = (IN + IP)/2 (31) Input offset current, IIO, is defined as the difference between the bias currents at the inverting and non-inverting inputs, IIO = IN - IP (32) Bias current is of concern when the input source impedance is high. Usually offset currents are an order of magnitude less than bias current so matching the input impedance of the inputs helps to nullify the effect of input bias current on the output voltage. 5.4 Input Common Mode Voltage Range Normally there is a voltage that is common to the inputs of the op amp. If this common mode voltage gets too high or too low, the inputs will shut down and proper operation ceases. The common mode input voltage range, VICR, specifies the range over which normal operation is guaranteed. Figure 5-2 illustrates the positive input voltage limit using the simplified op amp diagram of Figure 4-1. When VIN is higher than VCC - 0.9 V, the input transistors and the current source will begin to shut down. VCC + 0.3 V ± 2IE + + 0.6 V ± Q1 0.6 V ± Q2 VN + VP VIN VIN+ < VCC ± 0.3 V ± 0.6 V Figure 5-2. Positive Common-Mode Voltage Input Limit Figure 5-3 illustrates the negative input voltage limit using the simplified op amp diagram of Figure 4-1. When VIN is less than –VEE + 0.6 V, the current mirror (Q3 - Q4) will begin to shut down. SLOA011B – JANUARY 2018 – REVISED JULY 2021 Submit Document Feedback Understanding Operational Amplifier Specifications Copyright © 2021 Texas Instruments Incorporated 11 Op Amp Specifications www.ti.com VCC VN ± Q1 Q2 0V + + ± + 0V VP VIN Q4 VIN- > -VEE + 0.6 V Q3 + 0.6 V ± -VEE Figure 5-3. Negative Common-Mode Input Limit Structures like the one shown in the example above do not allow the common-mode input voltage to include either power supply rail. Other technologies used to construct op amp inputs offer different common-mode input voltage ranges that do include one or both power supply rails. Some examples are as follows (reference schematics can be found in the Texas Instruments’ data book, Amplifiers, Comparators, and Special Functions): • The LM324 and LM358 use bipolar PNP inputs that have their collectors connected to the negative power rail. Since VBC can equal zero, this allows the common-mode input voltage range to include the negative power rail. VCC Voltage range -VEE • The TL07X and TLE207X type BiFET op amps use p-channel JFET inputs with the sources tied to the positive power rail via a bipolar current source. Since VGS can equal zero, this structure typically allows the common-mode input voltage range to include the positive power rail. VCC Voltage range -VEE • 12 TI LinCMOS op amps use pchannel CMOS inputs with the substrate tied to the positive power rail. Therefore, a conducting channel is created for VG + VTH < VDD and this allows the common-mode input voltage to include the negative power rail. Understanding Operational Amplifier Specifications Copyright © 2021 Texas Instruments Incorporated SLOA011B – JANUARY 2018 – REVISED JULY 2021 Submit Document Feedback www.ti.com Op Amp Specifications VCC Voltage range -VEE • Rail-to-rail input op amps use complementary N and P type devices in the differential inputs. When the common-mode input voltage nears either rail at least one of the differential inputs is still active. VCC Voltage range -VEE 5.5 Differential Input Voltage Range Differential input voltage range is normally specified in data sheets as an absolute maximum. Figure 5-4 illustrates this. If the differential input voltage is greater than the base-emitter reverse break down voltage of input transistor Q1 plus the baseemitter forward breakdown voltage of Q2, then Q1’s BE junction will act like a zener diode. This is a destructive mode of operation and results in deterioration of Q1’s current gain. The same is true if VIN_DIFF is reversed, except Q2 breaks down. VCC 2IE VEBO = 5 V + ± + Q1 0.6 V ± Q2 VN + VIN_DIFF VP Q4 VIN_DIFF < 5.6 V Q3 + 0.6 V ± -VEE Figure 5-4. Differential-Mode Voltage Input Limit Some devices have protection built into them, and the current into the input needs to be limited. Normally, differential input mode voltage limit is not a design issue. SLOA011B – JANUARY 2018 – REVISED JULY 2021 Submit Document Feedback Understanding Operational Amplifier Specifications Copyright © 2021 Texas Instruments Incorporated 13 Op Amp Specifications www.ti.com 5.6 Maximum Output Voltage Swing The maximum output voltage, VOM±, is defined as “the maximum positive or negative peak output voltage that can be obtained without wave form clipping when quiescent DC output voltage is zero”. VOM± is limited by the output impedance of the amplifier, the saturation voltage of the output transistors, and the power supply voltages. This is shown in Figure 5-5. Note that VOM± depends on the output load. +VCC +VCC Voltage drop across R1 + VSAT And VBE of Q6 VBQ6 Q4 + + VBE6- VOM+ ± D1 R1 VD1D2 0V VO D2 R2 VOM- ± VI VBE7 + ± Q7 Voltage drop across R2 + VSAT and VBE of Q7 +VEE -VEE Figure 5-5. VOM± The maximum value that VBQ6 can be is +VCC, therefore VO ≤ +VCC – VR1 – VBEQ6 – VSATQ6. The minimum value that Vi can be is –VEE, therefore VO ≥ –VEE + VR2 + VBEQ7 + VSATQ7. This emitter follower structure cannot drive the output voltage to either rail. Rail to rail output op amps use a common emitter (bipolar) or common source (CMOS) output stage. With these structures, the output voltage swing is only limited by the saturation voltage (bipolar) or the on resistance (CMOS) of the output transistors, and the load being driven. Because newer products are focused on single supply operation, more recent data sheets from Texas Instruments use the terminology VOH and VOL to specify the maximum and minimum output voltage. Maximum and minimum output voltage is usually a design issue when dynamic range is lost if the op amp cannot drive to the rails. This is the case in single supply systems where the op amp is used to drive the input of an analog-to-digital converter, which is configured for full scale input voltage between ground and the positive rail. 5.7 Large Signal Differential Voltage Amplification Large signal differential voltage amplification, AVD, is the ratio of the output voltage change to the input differential voltage change, while holding VCM constant. This parameter is closely related to the open loop gain. The difference is that it is measured with an output load and therefore takes into account loading effects. The DC value of AVD is published in the data sheet, but AVD is frequency dependent. Figure 5-12 shows a typical graph of AVD vs. frequency. AVD is a design issue when precise gain is required. Consider equation Equation 16, where the loop gain of the non-inverting amplifier is given by: A VO VI 14 § · § 1· ¨ 1 ¸ ¸ ¨b¸ ¨ © ¹ ¨1 1 ¸ ¨ ¸ ab ¹ © (33) Understanding Operational Amplifier Specifications Copyright © 2021 Texas Instruments Incorporated SLOA011B – JANUARY 2018 – REVISED JULY 2021 Submit Document Feedback www.ti.com Op Amp Specifications where, b R1 R1 R2 (34) It is desired to control the gain of the circuit by selecting the appropriate resistors. The term 1/ab in the equation is seen as an error term. Unless a, or AVD, is large in comparison with 1/b, it will have an undesired effect on the gain of the circuit. 5.8 Input Parasitic Elements Both inputs have parasitic impedance associated with them. Figure 5-6 shows a model where it is lumped into resistance and capacitance between each input terminal and ground and between the two terminals. There is also parasitic inductance, but the effects are negligible at low frequency. Input impedance is a design issue when the source impedance is high. The input loads the source. Also input capacitance will cause extra phase shift in the feedback path. This erodes phase margin and can be a problem when using high value feedback resistors. ± VN CD VP CN RN CN RP RD + Figure 5-6. Input Parasitic Elements 5.8.1 Input Capacitance Input capacitance, Ci, is measured between the input terminals with either input grounded. Ci is usually on the order of a few pF. To relate Ci to Figure 5-6, if you ground Vp, Ci = Cd || Cn. Sometimes common-mode input capacitance, Cic, is specified. To relate Cic to Figure 5-6, if you short Vp to Vn, Cic = Cp || Cn, the input capacitance a common mode source would see to ground. 5.8.2 Input Resistance Two parameters for input resistance, ri and rid, are defined in Texas Instruments’ data book, Amplifiers, Comparators, and Special Functions, pg. 1-39. Input resistance, ri, is "the resistance between the input terminals and either input grounded." Differential input resistance, rid, is "the small-signal resistance between two ungrounded input terminals." To relate ri to Figure 5-6, if you ground Vp, ri = Rd || Rn. Depending on the type of input, values usually run on the order of 107Ω to 1012Ω. To relate rid to Figure 5-6, with both input terminals floating, rid = Rd || (Rn + Rp). Depending on the type of input, values usually run on the order of 107Ω to 1012Ω. Sometimes common-mode input resistance, ric, is specified. To relate ric to Figure 5-6, if you short Vp to Vn, ric = Rp || Rn, the input resistance a common mode source would see to ground. SLOA011B – JANUARY 2018 – REVISED JULY 2021 Submit Document Feedback Understanding Operational Amplifier Specifications Copyright © 2021 Texas Instruments Incorporated 15 Op Amp Specifications www.ti.com 5.9 Output Impedance Different data sheets list the output impedance under two different conditions. Some data sheets list closed-loop output impedance while others list open loop output impedance, both designated by Zo. Zo is defined as the small signal impedance between the output terminal and ground (see Amplifiers, Comparators, and Special Functions, pg. 1-40). Data sheet values run from 50Ω to 200Ω. Common emitter (bipolar) and common source (CMOS) output stages used in rail-to-rail output op amps have higher output impedance than emitter follower output stages. Output impedance is a design issue when using rail-to-rail output op amps to drive heavy loads. If the load is mainly resistive, the output impedance will limit how close to the rails the output can go. If the load is capacitive, the extra phase shift will erode phase margin. Figure 5-7 shows how output impedance affects the output signal assuming Zo is mostly resistive. ZO ZO Vo = aVd RL (RL+Zo) AVi RL 1 Vo = aVd (jf/fo) + 1 CL 1 Where fo = 2pi ZoCL AVi Resistive Load Capacitive Load Figure 5-7. Effect Output Impedance 5.10 Common-Mode Rejection Ratio Common-mode rejection ratio, CMRR, is defined as the ratio of the differential voltage amplification to the common-mode voltage amplification, ADIF/ACOM. Ideally this ratio would be infinite with common mode voltages being totally rejected. The common-mode input voltage affects the bias point of the input differential pair. Because of the inherent mismatches in the input circuitry, changing the bias point changes the offset voltage, which, in turn, changes the output voltage. The real mechanism at work is ΔVOS/ΔVCOM. In a Texas Instrument data sheet, CMRR = ΔVCOM/ΔVOS (gives a positive number in dB). CMRR, as published in the data sheet, is a DC parameter. CMRR, when graphed vs. frequency, falls off as the frequency increases. A common source of common-mode interference voltage is 50 Hz or 60 Hz noise from the AC mains. Care must be used to ensure that the CMRR of the op amp is not degraded by other circuit components. 5.11 Supply Voltage Rejection Ratio Supply voltage rejection ratio, kSVR (AKA power supply rejection ratio, PSRR), is the ratio of power supply voltage change to output voltage change. The power voltage affects the bias point of the input differential pair. Because of the inherent mismatches in the input circuitry, changing the bias point changes the offset voltage, which, in turn, changes the output voltage. The real mechanism at work is ΔVOS/ΔVCC±. In a Texas Instrument data sheet, for a dual supply op amp, kSVR = ΔVCC±/ΔVOS (to get a positive number in dB). The term ΔVCC± means that the plus and minus power supplies are changed symmetrically. For a single supply op amp, kSVR = ΔVDD/ΔVOS (to get a positive number in dB). Also note that the mechanism that produces kSVR is the same as for CMRR. Therefore, kSVR, as published in the data sheet, is a DC parameter like CMRR; when kSVR is graphed vs. frequency, it falls off as the frequency increases. Switching power supplies can have noise on the order of 20 kHz to 200 kHz and higher.