680 Scientific Computing System Reference Handbook
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SCIENTIFICCOMPUTINE SYSTEIUI
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RELATED PUBLICATIONS
The table below lists other publications which may be of interest to the readers of this manual.
Unless otherwise indicated by title or footnote, all are maintenance handbooks. Note that maintenance handbooks directly applicable to a particular
system are normally supplied with the sys-
tem.
Title
Fublieation Number
Handbook of Analog Computation
00 800.0001-3
8850 X-Y Plotter - Volume 1
8850 X-Y Plotter - Volume 2
00800.1133-0
00800.1134-0
8880 Display Unit
00800.1145-1
8875 Recorder - Volume 1
00800.1150-1
8875 Recorder - Volume 2
00800.1151-0
8875 Recorder - Volume 3
00800.1152-0
8881 Oscilloscope
00800.1153-1
680 Reference Handbook
00 800.2048-0
680 Console Components
00 800.2049-0
680 Computing Components
00 800.2050-0
680 Replaceable Parts Lists
00800.2051-1
680 Drawings - Volume 1
00 800.2052-1
680 Drawings - Volume 2
00 800.2053-1
680 Digital Voltmeter, Model 26.268
00 800.5027-0
_l
-1
-l
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NOTICE
In order to enable us to process your requests for spare parts and replacement items quickly
and efficiently, we request your conformance with the following procedure:
1.
Please specify the type number and serial number of
the basic unit as well as the EAI part number and description of the part when inquiring about replacement
items such as potentiometer assemblies or cups, relays, transformers, precision resistors, etc.
2.
When inquiring about items as servo multipliers, resolvers, networks, printed circuit assemblies, etc.,
please specify the serial numbers of the major equipment with which the units are to be used, such as:
Console, Type 8811, Memory Module, Type 4.204,
Serial No. 000, etc. If at aII possible, please include the purchase order or the EAI project number
under which the equipment was originally procured.
Your cooperation in supplying the required information will speed the processing of your requests
and aid in assuring that the correct items are supplied.
It is the policy of Electronic Associates, Inc. to supply equi,pmentpatternedas closely as possible to the requi,rements of the indiuidual castomer. This is accomplished, without incarring the
prohi'bitiue costs of castorn desi,gn, by substi.tuting new components, modifying standard components, etc., whereaer necessclry to expedite conformance withrequi,remenis. As a result,
this instruction manaal, o'ohichhas been uritten to coaer standnrd equipment, may rnt enti.reiy
concar inits content withthe eEtiy'ment supplied. It isfelt, hnweuer, tlnt atechnicatty quatified person will find the mavrual a fully adequate guide in understanding, operating, and maintaining the equipment actually supplied.
Electronic Associates, Inc. reserves
the right to make changes in design,
or to make additions to or improvements in its product without imposing
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ADVANCEDSYSTEMSANALYSTSAND COMPUTATIONSERVICES/ANALOG
COMPUTERSiDIG'TAL COMPUTERS/HYBRID
ANALOG.DIGITALCOMPUTATIONEQUIPMENT/ANALOGAND DIGITAL
PLOTTERS/SIMULATION
SYSTEMSi
SCIENTIFICAND LABORATORY
INSTRUMENTS/INDUSTRIAL
PROCESS
CONTROL
SYSTEMS/PHOTOGRAMM€TRIC
EQUIPMENT/RANGEINSTRUMENTA
TloN SYSTEMS/TEST
AND cHEcK'ouT sYsrEMs/MlLlrARY AND INDUsTRtALREsEARcHAND DEvELopMENTsERttaEs/FtELDENGTNEERTNG
AND EoutpMENr MATNTENANcE
sERvtcEs.
Printed in U.S.A.
Bulletin No. tL{4104-6
June,1966
I
CONTENTS
Page
CHAPTER tr.- INTRODUCTION
1. 1
PURPOSE OF THIS MANUAL.
1-1
L.2
BACKGROUND KNOWLEDGE ASSUMED
1-1
1.3
STRUCTURE OF THIS MANUAL
1-1
1..4 WHAT TO READ FIRST
CHAPTER 2 - GENERAL MACHINE ORGANIZATION
I
a
1-1
1-2
2-l
2.T
THE PATCH PANEL
2-2
2.2
THE OVERLOAD INDICATOR,S
2-2
2.3
THE LOGIC READOUT PANEL
2-3
2.4
THE HANDSET POT STRIP
2-5
2.5
THE ANALOG READOUT PANEL
2-5
2.6
THE CONTROL KEYBOARD
2-7
2.7
THE TEST POSITION
2-L0
2.8
THE VDFG AND LIMITER DRAWERS
2-10
CHAPTER 3 - THE SIGNAL SELECTOR,SYSTEM
3-1
3.1
THE COMPONENT SELECTION KEYS
3-1
3.2
THE TEN NUMERTCAL KEYS (0 - 9)
3-2
3.3
THE CONTROL KEYS (CL, DAC, INC, cO)
3-3
3.4
READOUT PROCEDURES
3-4
3.5
SEQUENTIALREADOUT
3-4
3.6
PATCH PANEL TERMINALS
3-5
3.7
SYSTEM BLOCK DIAGRAM
3-5
CHAPTER 4 - THE SERVO POT-SETTING SYSTEM
4-l
4.T
SETTING A POT FROM THE KEYBOARD.
4-L
4.2
EXAMPLE OF SEQUENTIAL POT-SETTING
4-2
4.3
MANUAL ADJUSTMENT
4-3
CONTENTS (Cont)
Page
4.4
MANUAL ADDRESSING.
4-4
4.5
CIRCUIT DETAILS.
4-4
CHAPTER 5 - PATCH PANEL LAYOUT
5.1
THE TRAY
5-1
5.2
ROWS, STRIPS, AND FIELDS.
5-2
5.3
THE TYPICAL ANALOG FIELD
5-3
5.4
THE LOGIC ROW
D-D
5.5
SUMMARY OF EQIITPMENT COMPLEMENT
5-6
CHAPTER 6 - THE COMBINATION AMPLIFIER
6-1
6.1
LOCATION AND ADDRESSING
6-1
6.2
PATCH PANEL LAYOUT
6-1
6.3
APPLICATIONS
6-3
6.4
MODE CONTROL AND CAPACITOR SELECTION.
6-3
6.5
CIRCUIT DETAILS
6-4
CHAPTERT -THESUMMER
7-t
7.L
THE TRACK/STORE SUMMER
7-L
7.2
THE LIMIT SUMMER
. J- D
CHAPTER 8 - THE POTENTIOMETER
8-1
8.1
SERVO-SET POTS
8-1
8.2
HANDSET POTS
8-2
CHAPTER I - FD(ED DFG's AND JUNCTION INVERTERS
It
5-1
9-1
9.1
THE JUNCTION INVERTER ...
9-1
9.2
THE LOG/EXPONENTIAL DFG
9-4
9.3
THE SrN/COSDFG
9-?
CHAPTER 10 - THE VARIABLE
10-1
10.1
LOCATION AND ADDRESSING
10-1
IO.2
APPLICATIONS
10-2
T
J
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II
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CONTENTS (Cont)
Page
1 0 .3
SETUPPROCEDURE....
t0-2
1 0 .4
CIRCUIT DETAILS
l0-20
CHAPTER 1 1 - T H E M U L T I P L I E R . . . .
1 1 -1
1 1 .1
LOCATION AND ADDRESSING
11-1
Lt.2
APPLICATIONS .
11-1
1 1 . 3 CIRCUIT DETAILS
11-1
CHAPTER12 - MISCELLANEOUSANALOG COMPONENTS ...
L2-l
t2.1
THE FEEDBACK LIMITER ..
12-t
12.2
THE NOISE GENERATOR. .. .
t2-3
t2.3
T]NCOMMITTED RESISTORSAND DIODES
t2-3
L2.4
TRUNK,S
t2-4
t2.5
REFERENCE, TEST REFERENCE, AND GROUND
t2-4
12.6
READOUT DEVICES
t2-5
CHAPTER13 - THE INTERFACE TRAY
13-1
1 3 . 1 LOCATION AND ADDRESSING
13-1
13.2
TH E ANALOG-TO.DIGITAL
COMPARATOR
t3-2
1 3 .3
THE DIGITAL-TO-ANALOG
SWITCH.
t3-4
t3.4
THE DIGITAL-TO-ANALOG
RELAY
13-4
CHAPTER 14 - THE GATE TRAY.
14-t
L4,t
LOCATION AND ADDRESSING
t4-l
t4.2
APPLICATIONS .
t4-l
CHAPTER1 5 - T H E G P R T R A Y
1 5 .1
....,..
15-1
LOCATION AND ADDRESSING
15-1
1 5 . 2 REGISTER INPUTS AND OUTPUTS ..
1 5- 1
1 5 . 3 FLIP-FLOP INPUTS AND OUTPUTS . .
15-3
L5.4
15-5
PROGRAMMER'S SYMBOLS .
tlI
CONTENTS (Cont)
Pa€e
1 5 .5
DISPLAY AND MANUAL CONTROL....
CHAPTER16 . THE BCD COUNTER TRAY
1 6 -1
1 6 .1
LOCATION AND ADDRESSING
16-1
t6.2
READOUT AND MANUAL CONTROL . . .
1 6 -1
1 6 .3
REGISTER TERMINATIONS .
t6-2
16.4
INDIVIDUAL FLIP-FLOP
16-3
1 6 .5
PROGRAMMER'SSYMBOL ..
TERMINAI.S
CHAPTER1?- THE MONOIDIFF TRAY
t7.L
LOCATION AND ADDRESSING
16-3
L 7- L
1?-1
1 7 . 2 THE MONOSTABLE TIMER
t 7- t
1 7 .3
17-3
THE DIFFERENTIATOR
CHAPTER 18 - IVIISCELLANEOUSLOGIC COMPONENTS...
1 8 -1
1 8 . 1 TRUNKS
1 8 -1
1 8 . 2 s c o P E S , P L O T T E R S , A N D R E C O R D E R S. . . .
1 8 -1
1 8 . 3 DIGITAL PUSHBUTTONS..
1 8 -1
CHAPTER19 - ANALOG TIME SCALE CONTROL
1 9 -1
CHAPTER20 - ANALOG MODE CONTROL
20-1
20.L
MANUAL AND LOGICAL CONTROL ....
20-1
20.2
NORMAL REPETITIVE OPERATION ..
20-1
20.3
FUNCTIONS OF THE TERMINALS IN THE TIMER TRAY .....
20-2
20.4
CIRCUIT DETAILS
20-6
CHAPTER21 - LOGIC MODE AND CLOCKRATE CONTROL
tv
15-5
2t-L
2l,t
THE LOGIC MODES
21-L
21.2
CLOCK RATES
2L-L
2t.3
LOGIC DIAGRAM
2t-L
t
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1
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CONTENTS (Cont)
Page
APPEND;
1 - ANALOG SYMBOLS AND PATCHING
A1-1
1.1
INVERSION
A1-1
t.2
INTEGRATION
A1-2
1.3
SUMMATION
AL-4
t.4
POT FEEDBACK
A1-6
1.5
TRACK/STORE OPERATION
A1-9
1.6
HIGH-GAIN AMPLIFIERS
A1-13
1.7
ZERO LIMITING.
A1-13
1.8
FEEDBACK LIMITERS
A1-15
1.9
POT APPLICATIONS
1.10
MULTIPLICATION.
A1-18
1 .1 1
DIVISION
At-20
1.12
SQUARING
A1-20
1.13
SQUARE ROOTS
A1-23
1.74
GENERATING-xlxl.
AL-24
1.15
GENERATING-(sign x) .m
At-24
1.16
THE LOG FUNCTION
A1-24
L.77
THE EXPONENTIAL FUNCTION.
At-27
1.18
THE SINE FUNCTION
At-27
1.19
THE COSINE FUNCTION
A1-29
1.20
I].N/ERSE TRIG FUNCTIONS.
AL-29
I.2l
ARBITRARY FUNCTIONS.
A1-30
r.22
UNCOMMITTED RESISTORSAND BORROWED NETWORIiS ..
A1-31
L.23
THE A/D COMPARATOR
A1-32
1.24
ELECTRONIC SWITCHING.
A1-32
L.25
RELAY SWITCHING
At-34
A1-17
CONTENTS (Cont
Ess
A2-L
APPENDD( 2 - EQUIPMENT ASSIGNMENT SHEETS
2.I
AMPLIFIER SHEETS
A2-t
2.2
P O T E N T I O M E T E RS H E E T S . . . . . , .
A2-t
2.3
NONLINEAR COMPONENTS AND HANDSET POTS .
A2-6
2.4
LOGIC SHEET AND INTERFACE SHEET
A2-6
A3-1
APPENDD( 3 - STARTUP PRObEDURE ....
vl
3.1
APPLYING POWER
A3-1
3.2
INSERTING THE PATCH PANEL
A3-1
APPENDD( 4 - USES OF THE LOG/EXPONENTIAL DFG..
A4-l
4.I
BASIC EXPONENTIAL CIRCUIT....
A4-2
4.2
WIDE-RANGE EXPONENTIAL
A4-3
4.3
EXPONENTIAL WITH ARBITRARY SCALE FACTOR
A4-4
4,4
GENERATING FRACTIONAL POWERS ...
A4-ä
4.5
MULTIPLICATION WITH BUILT-IN SCALE FACTOR
A4-6
4.6
MULTIPLICATION WITH ARBITRARY SCALE FACTOR.....
A4-7
4.7
P R O D U C T SO F P O W E R S . . .
A4-8
4.8
DIVISION
A4-9
4.9
R E C I P R O C A I S. . .
A4-10
4.10
BASE 10 LOGS
A4-11
4.II
I L L U S T R A T I O NO F A D U A L C I R C U I T
4.I2
LOGIEXPONENTIALTABLES
......
A4-11
A4-t2
APPENDD( 5 - ELECTRONIC SWITCHES..
A5-1
APPENDD( 6 - NORMALLY-CLOSED PATCH PANEL SWITCHES
A6-1
APPENDX ? - STANDARD 680 PATCH PANEL CONFIGURATION .
A7-1
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ILLUSTRATIONS
Figure
Number
Title
2.1
Ouerqll View of the 680
9
9
The Log,ic Read.out pqnel
9
2
The Arnlog Readout panel .
2-1
2-3
2-5
2.4
The Control Keyboard
2.5
A Combination Amptifier in the Test position.
....
2-11
3,1
Si.gnalSelector, Block Diagram ....
3-6
4.1
Logic Diagram of Seruo pot-Setting SysteTrt
4.2
Indi,uidual pot Addres sing Circuitry
5.1
A Typical Tray and. Its patching Area.
5-1
5.2
Patch Panel Layout, Shnwing Rows, S.trips,
and.Fields
5-3
5.3
Detqiled Patch panel Layout
2-8
6-2
6-5
'
Si.mplified Schemqtic of a Combi.nation Amptifier
A
2
simplified schematic of capacitor serection circaitr,
7,1
Patching Area for Track/Store
7.2
Simplifi. ed Schematic of Tr ac k/ Stor e Sotmmer
7
P a t c h i n gA r e a f o r L i . m i t 9 u m m e r . . . . . . . . ,
7.5
Simplified Schematic for Limit Summer ,
,I
7.6
Equiualent Circaits of Limdt Summer, with
8.1
Seruo-Set Pot Locations Within a Field
8.2
Normally - Clo s ed Cotarccti.ons on pots
Q
Simplified Schematic, Junction Inu erter
)
1t
)
;
a
1
o-/
Summer .
Typical Applications of the Li.mit Summer
I
I
4-6
A
?
4-C
5-4
l
J
,..
Patch Panel Layout for Combination Am\tifier.
7.4
I
Page
7-2
.
7-4
7-6
...
7-7
7-8
Bottteph.tg Inserted . ....
9.2
Junction Inaerter patching Areas
o e
Use of the Junction Inuerter as a DFG Outtut
Amplifier
7-8
8-1
8-2
9-1
9-2
.
9-3
ILLUSTRATIONS (Cont)
Figure
Number
vtll
TitIe
Page
q 4
Siruplified Schematic, Junction Inuerter with Zero Limi.ti.ng
9-4
9.5
The Log/Exponential
9-5
9.6
Patching Termiymtions for Sin/Cos DFG
9-8
10.1
Vqri.able DFG Patching Tet'minations .
10-1
10.2
Ty|ical
70-4
70.3
Effect of Changing Slope Pot 5 on DFG Outtut
70-5
10.4
DFG Setup Panel (In UPPer DFG Drawer)
1-0-7
10.5
Typical DFG Drawer (Except for UPPer Drawer)
70-8
10.6
Ty Dical Func ti on R eq.r.iring Slof e Am blifi c ati on
10-13
10.7
Initi.ally Horizontal El euen- Segtnent Function
10-75
L0.8
A Typical Twenty-Segment Function
10-18
10.9
Typi.cal Ci.rcuitry for One Segment
10-20
1,0.1,0
10/20/INV
Switching
10-21
10.11
Setup Panel Ci.rcui.try
10-23
11.7
Quarter-Square Multiplier
Patching Areq. .
11 -2
1 1, 2
Quarter-Square Multiplier
Eqtiualent Schematics . . .
11 -2
12.1
Patching Termi.rntions for a Feedback Li.miter
12-1
12.2
Feedback Limiter
12-2
13.1
Interfac e Tray Termirwtions
13-1
13,2
Block Diagram, Electronic Comparator ..
1 3-3
13.3
Relay Equiaalent of D/A Electronic Switch'
14,1
Patch Panel Termi.rntions and Programrnerts
Gates .
DFG Patching Terminations
.
Ten-Segm ent Function
...
SetuD Controls in Sli.deout Drawer
t,
73-5
Symbols for AND
14-1
14.2
Using an AND Gate for the OR Functi.on
14-2
15.1
Patch Panel Termirations for a Gensral-Purpose Register ......
15-1
ILLUSTRATIONS (Cont)
Figure
Number
TitIe
Page
15.2
Internal Connections for the nLoadn and ,,Erutblet,
Inputs
15.3
Programmerts
16.1
Patchi.ng Termiywtions for BCD Counter
16.2
Programrnerts
17.1
Patch Panel Terminations
17.2
Programmer ts Symbol for Moynstable Timer
1 7- 3
17.3
Programm er ts Symbol for Differentiq.tor
17-3
18.1
Programmer Is Symbol for Digitat pushbutton
19.1
M a s t s r q . n d l n d i u i . d t t aTl i . m eS c a l e C o n t r o l
20.1
Mode Control/Timer
20.2
Timing pulses and Rep-Op Timer
20-6
20.3
Mode Register and Mod.e Control Logic.
20-7
21.1
Logic Diagram of the Logic Mode and Clock
At. L
Programmer,s Symbols for Inuerter,s ....
4L-1
47.2
ffandard Patching and Symbols
for an Integrator
A1-s
r''7.3
Integrator with Ten Tirnes Normal Gq.in.
.
AL-3
41.4
Integrator with rc/Op
AJ.5
Abbreuiated Symbot for the Integrator in Figure
Aj.4
r'-l.6
Summation with q Track/Store
41.7
Summation with a Limit Summer . ..
.., ...
41-5
A1.B
Sotmmationwith a Combirati.on Amplifier
. ... ..
At_-6
41.9
Usi.ng the Trqck/S'tore Summer with pot Feedback
At-7
r'^l.10
Using the Limi.t Summer with pot Feed.back
47-8
Symbol for a Flip_Ftop arui a Register
1 6- 3
for Mono,/Diff Tray .
1 7-1
.
....
18 -1
..i...
.
Using the Combination Amplifier
1^1.12
Conuentional Track/Stor e Unit
19 -2
20-2
Rate Control ......,.
Mode Cycling From a Singte Logic Source..
,4-1.11
15-5
1 6- 1
Symbol for BCD Counter
Tray
15-4
Summer
.
21-.2
A7-4
A1-4
41-5
.. . .
with pot Feedback
41-8
A1-9
ILLUSTRATIONS (Cont)
Figure
Number
Page
TitIe
A1-10
Unit uith Pot Feedback .. . .
41.13
Track/Store
41.L4
Track,/Store Unit with Arbitrary
4L.15
usi'ng the combi'nnti'on Ampti'fi'er as a Track/store
4J.76
(Jsing the Juncti'on Inuerter as a Hi'gh-Gai'n Ampli'fier " " '
A7-13
4t.77
tlsi,ng the Li'rni't Summer as a Hi,gh-Gai,n Amplifier
A7-74
A1.78
(Ising the Track/Store
41.19
Using the Cornbi,rwtion Arn\tifi'er
41.20
Limiting
41.27
Feedback Limi'ter, Symbol and Patching
A1-16
41.22
Two-Terminal Pot, Typical Symbol and Patchi'ng
A1-17
4L.23
Three Terminal Pot, Typical Symbol and' Patching
A1-17
47.24
Iv[ulti\lier
41.25
Mutti\lication
A1.26
gtmbol and Patghi,ng for Diui'si'on
41.27
Squaring u/ith DFG 7 and Associ'ated Ampli'fi'er .. ..
A1-22
A1.28
Squari.ng with DFG 1 and Another Am|lifier
A1-22
41.29
Square Root Circait, DFG 2 ....
A1-23
4L.30
G e n e r a t i n g- x t x l .
A1-25
Al-.31
Generating -(sisn xtffi
47.32
Logarithm,
Using the +Log Network ....
A1-26
41.33
Logarithm,
tlsi.ng the -Log Network ....
A1-26
41.34
Exponenti.al, Usi'ng the +Netaork . . . .
47.35
Symbol and Patchi,ng for
A1.36
Programmer's
4J..37
Symbot and Patching for Inuerse Sine Ft'r'ncti'on. . . . .
At-11
Feedback
A7-12
unit '
'''" " '
AJ.-14
as a High-Gain Amplifi'er " " " '
AJ -L5
Summer as a High-Gain Am\lifier
the Limi.t Summer to Positi'ue Otr't|uts
Al -L6
A1-78
Symbols and Patcbing
AL -19
with Pot Feedback . . . -
A7 -20
...:..
AL-25
'l
-Si.n0
SYmbolfor +Cos9
AL-27
A7-28
A1-29
A1-30
I
JI
h
h
5
I
I
I
ILLUSTRATTONS (Cont)
Figure
Number
Tiile
3S
A1.38
Inaerse Sine Function with pot Feedback ....
41,.39
Arbitrary
41.40
I IBo,t l,oaoed t,
41,41
Programmerts
Symbol, Electronic
41.42
Programmer,s
Symbol for D/A Switch . . .
r'.l.43
use of the hmbinqtion Amptifier as an Erectronic
41-30
Function Genq,qtion
Resi.stor
41-31
Netaork
Af -32
Combarator
A1-32
AJ -33
sr,oitch
tIl-
-5c
41.44
Use ofthe D/A Relq.y (with Complementary Input)
41-35
4J.45
Use of the D/A Relay as a Latching Relay .
41-35
42.1
Amplifier Assignment Sheet (A0-A5g) ,..
A2-2
42.2
Amplifier
Assi.gnment Sheet (A60-4119) ...
42-3
42.3
Potentiom eter As signment Sheet (p00 _p|g)
42-4
42-5
I
42.4
Potentiometer As signment Sheet (p60 _pl 1 g)
.)
42.5
Nonl_inear Component As signn t ent Sheet, (Muttiplier
s, DF G,s,
Limiters and Handset pots),
\
42.6
Logzc Assignment Sheet
1
42.7
Ircterface Assignment Sheet .
A2-9
44.1
Basic Exponential Circait ....
A4-2
44.2
Circait Diagram for Scaled Example
A4-s
A4.s
Exponential with Arbitrary
44.4
Generating Nth power
44.C
Mt r.ttiplication - Single Amplifier
44.6
Multiplication
44.7
Multiplicati.on with Arbitrary
-T
44.B
Products of pouters
t
44.9
Diaision
t'
t'L
I
t
q
I
l_
42-7
42-8
Scale Factor
44-4
A4-J
- Many prod:ucts with
44-6
Common Factors
Scale Fqctor .,..
A4-6
44-7
44-8
44-9
xr
ILLUSTRATIONS (Cont)
Figure
Number
xu
Page
44.10
Reciprocal Generation
A4-10
44.11
Base 70 Log ..
A4-11.
44.12
Illustration
46.1
Normally
46.2
Norrnally Closed Switch with Patchcord Inserted
46.3
Normally
46.4
Norrnally -Open Switch lilitlmrt Patchcor d
46.5
Normally-Open
Switch with Patchcord (or Pin) Inserted . . , . . .. . .
46.6
Narmally-Open
Diagrams
Patch Panel Switch as it Appears on Schematic
of a Dual Circait.
Closed Switch withnut Patchcord.
Closed Switch as i.t Appears on Schematic Diaglarn's. . ..
44-71
A6-L
A6-1
A6-7
A6-1
A6-L
A6-1
l
CHAPTER 1
INTRODUCTION
1.1
PURPOSE OF THIS MANUAL
This manual is intended to fill two specific needs: The need for a text for the programmer to
study to familiarize himself with the computer, and the need for a reference book for the experienced programmer to look up an occasional circuit. To accomplish these goals,
the main
body of the book (Chapters 1 through 21) is written in "textbook" format, covering each component in turn. The reader interested in rapidly learning how to use a given component
should
read only the initial paragraphs of each chapter, and skip the paragraphs marked,'Circuit Details",
which contain schematics, block diagrams, and other information on the internal hard-
wate.
Explicit patching diagrams and suggested programmer's
symbols for analog components are
given in Appendix 1, which is organized somewhat differently from the rest of the book. The
rest of the book is organized by componeals,'Appendix 1 is organized by apptications.
I.2
BACKGROUND KNOWLEDGE ASSUMED
This handbook is intended to provide the experienced analog programmer with a description of
the specific features in the 680. Familiarity with analog computation in generalis assumed.
Hence, no information on programming and scaling is included, with one principal exception.
This exception is Appendix 4, which covers the log/exponential DFG, and includes a considerable amount of sbalng detail, since most textbooks on analog computation do not cover log,/exponential scaling adequately.
1.3
STRUCTURE OF THIS MANUAL
The manual may be divided into three main subdivisions, exclusive of appendices:
1.3.1
C h a p t e r s2 t h r o u g h 5
These chapters contain basic programming and operating information for the computer as a
;
whole.
L.3.2
C h a p t e r s6 t h r o u g h 1 8
These chapters contain descriptions of individual components. Each chapter covers a single
component or a group of closely related components.
1-1
680 REFERENCE HANDBOOK
1.3.3
C h a P t e r s1 9 t h r o u g h 2 1
and time scale selection' This information
These chapters contain information on mode control
problems' but can be quite useful for repetitive
is not necessary for simple, straightforward
20.3 contains descriptions of a number of
and iterative operation. In particular, Paragraph
are occasionally useful'
mode control and overl0ad detection features which
1.4
WHAT TO READ FIRST
L. 4.L
Basic Information
For the reader who is just starting out, and wants
blem, the following reading is recommended:
to "get on the computer" for a simple pro-
t.4,L,LRead'Chapters2throughs.Theseparagraphscontainbasicmaterial
'where
to find things", and how to set up the problem'
on
|,4.|.2ReadAppendix6,whichexplainstheuseofnormally-closedpatchpanel
throughout the manual' and are essential
contacts. These contacts appear in many schematics
Even the reader who is not "schematic-oriented"'
to understanding many of the patching features.
should examine this appendix' and Figure
but simply wants to know how to patch the components,
pot feature can result in considerable patching simpli8.2. Proper use of the normally-connected
Inverter (Figure 9' 3) requires a knowfication. Similarly, a full understanding of the Junction
operates'
Iedge of how the normally-connected feedback resistor
to the applications
Read the paragraphs in Appendix 1 which correspond
of the corresponding chapfor the particular problem, and read the initial sections
t.4,t.3
you require
ters. Refer to the photograph of the patch panel in
1.4.L.4
t. 4.2
Appendix 7'
Read Appendix 3 (Startup Procedure)'
Further Information
of the machine and has run one or two
Once the programmer has obtained a basic understanding
especially Paragraphs 20' 1'
problems, a reading of chapters 19 through 21 is recommended,
at least skimmed, with the possible excep20.2, and 20,3. AII appendices should be read, or
tionofAppendix4(iftheprogrammerhasnointerestinlogsorexponentials).
discretion' In particular, the paraThe balance of the book may be read at the programmerrs
to some programmers and of little
graphs marked "circuit Details" may be of great interest
or no interest to others.
t-2
I
-I
-1
-1
-l
-]
CHAPTER 2
GENERAL MACHINE ORGANIZATION
An overall view of the 680 Console is given in Figure 2.1.
are briefly described in this chapter.
The major portions of the console
More detailed information is given in subsequent chap-
ters.
,
,::,:r::':f99tG':..,,
,,.,1;RHAS$tt?',',,,
,,f;,*!|f,! :; ,,:
;.::.11
.,fst*aPTsR,,.e,l
'WEfit-$Ä$,,
tNtlC*fSRS
{cIIAFTER.2}
-]
I
-]
I
f
f
t.:!i:i\\a
r::i::i:i?:1;
J t'.
:
:
!
!
CONTROLKEYSOARD
(CHAPTERSö A!*D4}
"ilxtTFR$ l#,:
UPPERDRAWER
( C H A P T €R I O )
I
!
Figure 2.7.
Ooer(rll View of the 6g0
2-t
:
E
680 REFERENCE HANDBOOK
2.T
THE PATCH PANEL
The patch panel is divided into five rows.
flops, counters, gates, etc. ).
The upper row is devoted to logic elements ({lip-
The lower four rows contain the analog elements. Almost all
computing components are housed in slideout trays direcily behind the panel.
F.
i:
E,
Further informa-
tion on the patch panel organization is given in Chapter 5.
f',
1..
il
The panel is of aluminum, and has a total of 4080 holes.
i:.
3.
sertion and removal.
::
A motorized drive is provided for in-
See Appendix 3 for the procedure.
t--.
$,'
F
Sl
2.2
THE OVERLOAD INDICATORS
t.
ä'
Sl
*,
Directly above the patch panel are the overload indicators (Figure 2.1).
overloads, the appropriate light on the overload panel glows.
for the amplifiers
are laid out in four rows, similar
When a component
Note that the overload indicators
to the layout of the patch panel itself.
first two digits are common to a block of ten amplifiers,
The
and only the last digit lights up. A
similar arrangement is used for the VDFG's and multipliers.
2.2.1
OverloadCriteria
An.amplifier is regarded as overloaded when its summing junction departs from virtual ground.
This usually means that the output has been driven beyond its normal operating range.
Most
amplifiers are capable of producing outputs up to about 1.2 or 1.3 units (12 or 13 votts) before
overloading.
A VDFG is regarded as overloaded for the purpose of triggering the alarm when
its output exceeds 1.05 units (10.5 volts) in magnitude. A multiplier is regarded as overloaded
when the sum of the absolute values of the inputs exceeds 2.05 units (20. 5 volts).
Note that for
this to happen, it is necessary, but not sufficient, tlat at least one input be greater than 1.0
unit.
Under some conditions, an input greater than reference voltage can be multiplied by a
smallerinputcorrectly. Forexample,if X=L.25 units(12.5volts)andY=0.6unit(6.0
volts), then lXl + lVf <2. OS. The muttiplier will not indicate an overload, and the output product will be correct (t0. ?5 unit, or t7. 5 volts). Thus the overload system is designed to respond only to genuine overloads.
Overload indication is also provided for the TREFERENCE power supplies.
A malfunction or
(such
excessive loading
as accidentally patching reference to ground) causes an overload indication.
2-2
-l
CHAPTER 2
It
q
2.2.2
GENERAL MACHINE ORGANIZATION
Audible Overload Alarm
In addition to the visual indication, an audible alarm is provided to which produces a tone whenever any component overloads.
A volume control is provided for this alarm behind the Iogic
readout panel. The volume may be varied continuously from an inaudible level up to one so loud
tfiat it may be easily heard in a room fuII of people and machinery.
II
!-1
-1
2.2.3
Logic Level and Control
In addition to the visual and audible alarms there is an output on the logic panel which comes
high whenever any component overloads.
Iogieal control.
2.3
A stored overload feature is also provided, under
For details on these features, see paragraph 19.3. ?.
THE LOGIC READOUT PANEL (Fisure 2.2)
This panel contains indicators that show the state of each logic element. When the element is
in the ONE state, the corresponding indicator is lit. Most of those indicators are pushbuttons
as well, allowing the logic element to be set or reset manually.
A listing of the indicators and
controls is given below. More detailed information is given in the chapters on the individual
components.
:l
1
tJ
coitTFotsJ
FOR MOJ{OSTABLE
TIMERS
(FARA2.3.2l
Figure 2.2.
t_ _t t_
t*ps61141DIGITAL
PUSHBUTTO}IS
{PARA2.3_3}
PUSHBUTTON/
II\IOICATORS
FOR
RfGISTERS
{PARA 2.3.5}
The Logic Req.dout panel
2-3
680 REFENENCE IIANDBOOK
T h e C o u n t e r s ( S e eC h a p t e r 1 6 )
2.3.1
Controls are provided for three BCD counters, each with two decades. The eight flip-flops in
each counter are individually displayed so that the contents of the counter may be determined
at any time by adding the numbers on all indicators that are lit.
buttons which may be used to manually set any given flip-flop.
each column allow mariual clearing.
The indicators are also pushPushbuttons at the bottom of
At the top of the panel, a pair of thumbwheels is provided,
to allow an initial value to be loaded into the counter.
The Monostable Timers (Seealso Chapter 17)
2.3.2
A thumbwheel and vernier pot, used for setting ttre time interval, are provided for each of the
six monostable timers.
Digital Pushbuttons (Seealso Chapter 18)
2.3.3
Six general purpose pushbuttons are provided.
output terminal on the patch panel.
Each button provides a ZERO or a ONE at an
Each output corresponds to a pair of buttons. Depressing
the button on tfie left sets the output to ONE; depressing the button on the right sets the output
io ZERO.
The button on the left acts as an indicator; it is lit when the output is set to ONE.
This output is not synchronized with the system clock.
When the output is set to ZEPrO, a
synchronized blip (a pulse one clock period in length) is generated at the output terminal each
time the button on the right is depressed. The complementary output is also terminated.
2.3.4
The AND Gates (Seeaiso Chapter 14)
Each AND gate in the computer is provided with an indicator which lights when the gate output
is logic ONE.
Each indicator is also apushbutton.
Depressingthe button has vn effectonthe
gate output. Since the gate is not a "memory" device, it is not possible to "SET" or "RESET"
it. However, depressing the button will tight the light as long as the button is held down. This
feature provides a quick check for a burned-out bulb.
2.3.5
The Registers (Seealso Chapter 15)
Each GPR (General-Purpose-Register) contains four flip-flops.
For each flip-flop,
there is a
pair of pushbuttons. The button on the left serves as an indicator; it lights when the flip-flop
is set.
It may also be used for manual control; depressing it sets the flip-flop.
the button on the right resets the flip-flop.
2-4
Depressing
I
5
h
I
h
l
!
IT
-I
-I
1
h
I
I
1
CHAPTER 2
2.4
GENERAL MACHINE ORGANIZATION
THE HANDSET pOT STRIP (Figure 2.3)
This strip contains the twelve handset pots. They are ten-turn,
bK pots, with locking knobs.
See Paragraph 8.2 for further details.
2.5
THE ANALOG READOUT PANEL (Figure 2.3)
This panel contains the DVM display, display for comparators
and function relays, and other
controls.
HANDSäT
POT S.TRIP.
{PARAE.4}
DVM
DISPLAY
(PARA
e.S,r)
COMmRATOft,
DTSPLAY
AND
coillTRoLs
(PARAa.5.2'
L{
REP-OP
T
n[r€R (
cosrTRo{-s
l
(PARA
1
J
e5.5)'"
MAHUAL POT.
SETTIN6
cor{Tfiol-s
(PARAa.5.61
MAIN POtl|Eft
sw!TcHEs
tiena a.6.sl
PATCH PANEL
DRIVgSWrTct"r€,s
(PARA2.5.4)
Figure 2.3.
H,-
The Awlog Readout panel
z-c
680 NEFERENCE HANDBOOK
2.5.t
The DVM Displav
This displays the address (e. g. , A25) and value (e. g. , +. 5942) of whatever component is
addressed on the signal selector.
(See Chapter 3 for a description of the signal selector. )
Values are displayed on a unit-scaled basis; that is, reference voltage is taken as the unit of
measurement. Hence, plus Reference is displayed as +1.0000 unit.
A x20qooverrange is pro-
vided; i. e., the DVM will measure values up to +1.1999 units (r11.999 volts).
2.5.2
The Comparators and Function Relays (See also Chapter 13)
A pair of buttons is provided for each of the 24 comparators in the computer.
The button on the
left is an indicator; it lights when the comparator output is ONE. Depressing this button will
set the output flip-flop,
forcing the comparator output on the patch panel to ONE regardless of
the state of the analog inputs.
Similarly,
depressing the other button forces the output to ZERO.
When the finger is removed from the button, the comparator reverts to normal operation, following its analog inputs. Of course, if the LATCH input is high, or the clock is in the STOp
mode, the analog inputs have no effect (see Paragraph 13.2) and the comparator output remains
in the state to which it was manually set.
This feature is useful for checkout. since it allows
the establishment of test signals at the comparator outputs.
A similar arrangement is provided for each of the 24 function relays. When a relay is in the
'r+" state, the button on the Ieft is lit. This button,
when depressed, forces the relay into the
"+" state independently of the patched Iogic inputs.
The button on the right, when depressed,
forces the relay into the "-" state. These relays are driven by flip-flops,
so that if no logic
signal is patched in, they remain in the state into which.tley are manually set. Hence, if no'
logic inputs are patched, the relays may be used as manual function switches.
2.5.3
Main Power Switches
These switches apply power to the computer.
the OFF button turns it off.
2.5.4
Depressing the ON button turns the.computer on;
For startup procedures, säe Appendix 4.
Patch Panel Drive Switches
These switches, marked ENG and DIS are for insertion and removal of the motor-driven patch
panel.
2-6
See Appendix 4 for procedure.
CHAPTER 2
2.5.5
GENERAL MACHINE ORGANI ZAT ION
Rep-OpTimer Controls
These controls determine the duration of the computing intervals in theÄep-op mod,e. See
Chapter 20, Paragraph 20. 2 and 20.3 for details.
2.5.6
The Manual Pot SettinE Controls
In the lower left-hand corner of the panel are a pair of pushbuttons marked POT ADDRESS and a
setof thumbwheels marked MANUAL SELECTOR. Belowthe DVM is a lever marked POT CONTROL.
4.
2.6
J
T
l
i
l
l
l
l
l
l
l
-l
1
These controls allow manual setting of the servo-set pots.
Details are given in Chapter
For normal servo-setting operation, the POT ADDRESS should be in the KEYBOARD mode.
THE CONTROL KEYBOARD (Figure 2.4)
The Control Keyboard located on the shelf below the analog readout panel. Its main functions
are mode control, signal selection, and pot-setting.
From left to right, the buttons are as
follows:
2.6.1
Logic Mode Control and Clock Rate Selection
The four buttons markedST, 10, 105, and 106 select the clock rate for the synchronized Iogic
elements, They form a mutually-exclusive group. (OnIy one of the four is lit at a time. Depressing one button lights it and extinguishes the