EAI 180 Computer Operator's Reference and Maintenance Manual
hy 4
Vor pd r;
chy ww met
om ‘ IV Ny per
ih (ib db | REST eR ee
a | | eed
bhnustfDnnsesefl rg ren
| lll
mn “Gl
Bb.
’ | | i { !
i) Wa) my a i
FA 180 COMPUTER
OPERATOR’S REFERENCE AND
MAINTENANCE MANUAL
EAI-ELECTRONIC ASSOCIATES PTY. LTD. PRINTED IN AUSTRALIA. JULY 72
WRITTEN BY EAI-ELECTRONIC ASSOCIATES PTY. LTD., SYDNEY, AUSTRALIA.
f
So ee
Soe es
f
¥
3
NOTICE
When ordering or enquiring about spare parts and replacement units for your
180 Computer, we request that you use the following procedure.
\ Supply the Drawing Number and Circuit Reference which is listed in the
parts listing at the back of this manual and the model and serial numbers
of the computer. Without this information we cannot process your request.
2. If the item is a mechanical part or assembly which does not have the above
reference, please supply a full description and the model and serial numbers
of the computer.
If possible, include the purchase order or the EAI project number under
which the equipment was originally purchased.
Your co-operation in supplying the required information will speed the processing of
your requests and aid in assuring that the correct items are supplied.
It is the policy of EAl-Electronic Associates Pty. Limited to supply equipment
patterned as closely as possible to the requirements of the individual customer. This
is accomplished, without incurring the prohibitive costs of custom design, by
substituting new components, modifying standard components, etc., wherever necessary
to expedite conformance with requirements. As a result, this instruction manual,
which: has been written to cover standard equipment, may not entirely cover
modified equipment. It is felt, however, that a technically qualified person will find
the manual a fully adequate guide in understanding, operating, and maintaining the
equipment supplied.
EAI-Electronic Associates Pty. Limited
reserves the right to make changes in
design, or to make additions to or
improvements in its product without
imposing any obligation upon itself
to instal them on products previously
manufactured.
CHAPTER 1.0
CHAPTER 2.0
CHAPTER 3.0
CHAPTER 4.0
CONTENTS
INTRODUCTION
tt
b2
Introduction
General Description
OPERATING PROCEDURES
2.1
2i2
Initial set up procedure
Operating Instructions
2.2.1 Readout and Meter Control
2.2.2 Display and Mode Control
2.2.3 Digital Control
COMPONENT DESCRIPTION
3.1
3.2
3.3
Linear Components
Non Linear Components
Digital Components
MAINTENANCE
4.1
4,2
4.3
4.4
Main Frame
Linear Panel
Non Linear Panel
Digital Panel
PAGE No.
10
10
13
21
25
25
34
55
66
66
68
71
77
Sot aepuevases CONTENTS continued.
APPENDICES
Aalt Unit Scaling
A 2 Transfer function simulation
A 3 Representation of constraints
and non linearities
CIRCUIT DIAGRAMS
Trunks and Power Wiring
Power Supply
Auxiliary Power Supply
Meter Switching —
Mode Control
Integrator
Dual Summer
Overload Indication
Function Relays
Quad Comparator
Quad Multiplier
DFG
Digital Clock
Pot Bus Switching Circuit
Sin/Cos Generator
Log x Generator
Vector Generator
Free Function Generator
No.
No.
No.
No.
No.
No.
No.
No.
No.
No.
No,
No.
No.
No.
No.
No.
No.
No.
180-54
180-36/47A & D
180-57A
180-56A
180-37A
180-32A
180-33A
180-12A
180-46A
180-45A
180-31A
180-28A
180-30A
180-22A
180-62
180-63
180-61
180-64
&
RO: SR RSE RS) RO RE BS Re) BS URS
D
180-35D
2 STE ed se OR er bal Wd > a Sl >
PAGE NO.
80
80
82
85
88
89
91
93
95
97
99
101
103
105
107
109
111
113
114
115
116
Ly
CHAPTER 1
1.1 INTRODUCTION
Many problems encountered in scientific, engineering and educational work
involve mathematical equations or sets of equations whose solution in most
cases is difficult or practically impossible to obtain by the classical approach
to equation solution. The EAI-180 Analog Computer provides the technical
worker with a general purpose computer which permits the rapid solution
of linear or non-linear equations.
Although the analog machine is correctly termed a computer, it does not
perform its computations by serial calculations as does the desk calculator
or digital computer. Instead it performs the required mathematical
operations in a parallel manner on continuous variables. In the EAI-180,
as in most modern analog computers, the continuous variables are direct
current voltages. The electronic analog computer makes it possible to
build an electrical model of a physical system, where the voltages on the
24 computer represent the dependent variables of the physical system. Except
for a constant of proportionality, or scale factor, each voltage will behave
with time in a manner similar to the physical system variable. Thus, if the
vertical position of the center of gravity of an automobile oscillates with
time during a disturbance, then the voltage representing the height of the
center of gravity above the surface will also oscillate; if the temperature
of the coolant at the exhaust port of a condenser rises exponentially to a
steady value, then so will the voltage representing it on the computer.
It can be said that the actual system and the electrical model are analogous
in that. the variables which demonstrate their characteristics are described
by relations which are mathematically equivalent. The actual system has
thus been simulated because of the similarity of operation of the electrical
model and the physical system. This capability of the analog computer is
of great value in performing scientific research or egineering design
' calculations because it permits an insight into the relationship between the
mathematical equations and the response of the physical system. Once the
electrical model is completed, well-controlled experiments can be performed
SSeS
i fam oly
L
L
ag a Na
== Le hr!
ee
Se a
Ce
quickly, inexpensively, and with great flexibility to predict the behaviour
of the primary physical system.
Although the analog computer utilizes electronic components in its
operation, it is not essential that the user have an extensive knowledge of
electrical circuits. The EAI-180 is basically a set of mathematical building
blocks, each able to perform specific mathematical operations on direct
voltages and capable of being easily interconnected. By appropriately
interconnecting these building blocks, an electrical model is produced in
which the voltages at the outputs of the blocks obey the relations given
in the mathematical description of a physical problem.
Since our interest is frequently in the dynamic behaviour of physical
systems, the mathematical equations are usually differential equations having
time as the independent variable. In order to solve such equations, the
standard components of the computer must perform the following
operations: inversion, algebraic summation, integration with respect to
time, multiplication and division, and function generation.
The sequence of steps for constructing a dynamic model on an analog
computer requires first a mathematical description of the physical system,
usually in equation form. From this description the operator derives the
information necessary to set up a computer program for interconnecting
the computing components and determines the required initial conditions
and forcing functions. The computing components are interconnected with
wires called patch cords. The input and output terminations of the
computing components are brought out to a patch bay panel. The problem
is placed on the computer by patching and adjusting the problem para-
meters to the value of the first case to be investigated. Selected voltages
are applied to various components in the form of inputs or initial
conditions. These voltages are derived from a precise reference voltage.
Once the computing elements have been patched, adjusted, and energised,
the computer is switched into the operate mode. The voltages on the
computer change with time in accordance with the equations that govern
the physical system variables. The behaviour of the computer model is
viewed through an output device such as an X-Y plotter, oscilloscope,
Tad
strip-chart recorder, or digital voltmeter,
The EAI-180 Operator’s Reference and Maintenance Handbook has been
prepared to serve as a working guide to the analog programmer or
computer operator. The information contained presupposes a knowledge of
the analog computer, its basic principles of operation, and programming
procedures. (Instructional information in these areas can be obtained from
“Basics of Analog Computer Programming” by the EAI Education and
Training Group). Readers interested in more detailed circuit information
are referred to the Maintenance section of the manual.
GENERAL DESCRIPTION
The EAI-180 (figure 1) is a general purpose analog computer composed of
solid-state computing components. The EAI-180 is compact in size and is
able to operate with stability and precision in a normal office or classroom
environment. Reliable, with simplicity in functional design, the EAI-180 is
easy to use and can be powerful aid to the individual engineer or student
in the rapid solution of scientific and engineering problems.
Table 1 (page 25) lists the currently available computing components and
accessories for the EAI-180. The EAI-180 utilizes a building block
concept, in which individual computing components may be easily inter-
connected to solve the required equations by forming electronic models
analogous to the system under study. Each building block, either individually
or in combination with others, is capable of performing one or more
mathematical operations. The computing components in the EAI-180
occupy the area to the left of the control panel area. This area is divided
into three rows; the top row contains linear components, summers and
integrators; the middle row houses the non-linear components and potentio-
meters; the bottom row contains Logic components. The computing
components are constructed on plug-in cards, and the front of each
computing component consists of a color-coded plastic patching overlay
that contains the input and output termination for the unit. The computing
components are inter-connected by placing patch cords -or bottle plugs
between the appropriate input and output terminations. The patching layout
of the EAI-180 has been designed to be compatible with larger EAI
computors so that experience gained on the EAI-180 can be readily trans-
ferred to larger machines.
To the right of the patching area is the monitoring and control area which
contains controls and components that permit the control of the computer
and its modes of operation and the measurement of problem variables.
The EAI-180 is completely tested and calibrated at the time of manufacture
and is shipped with all components in place. After performing the
preliminary check-out procedure outlined in the EAI-180 Maintenance
Manual, the computer is ready for operation.
It should be noted that the low voltage levels used in the EAI-180
eliminate any shock hazard to the operator when patching components with
the computer turned on. Current-limiting circuits protect the reference
supplies, and amplifier outputs from damage during short-term overloading
if they are inadvertently patched to ground or to each other.
‘UAL SUMMER
ad lees
seeeese
OVERLOAD INDICATORS
Seksmnbitahiaian easel
ANALOG-HY
BRI
7 ew Now
pondeete
HONAO |
BL} uO +
s=O*
HE EAI-180
D COMPUT
(vol
oe a et a
oe ge ea re a ea ere aes ee es ee ree
21
CHAPTER 2
OPERATING PROCEDURES
INITIAL SET UP PROCEDURES
In order to ensure that the equipment will function correctly, it is
advisable that the following initial set up procedure be followed before
the equipment is switched on.
Fl |
vA
2.3
Rating
Check that the equipment is correctly rated for either 240V,
SOHZ or 110V-60HZ operation. This information is displayed
on the rating plate located on the back of the computer,
Integrator Mode
Check that all integrators have dual bottle plugs connecting
control signals A and A to OP & R busses respectively.
Integrator Feedback
Check that all integrators have a 1 MF capacitor connected
in the Feedback loop. A single bottle plug may be used for
this purpose, connecting to the input/output positions indicated
by ‘1’ (the capacitor positions are 1 & 100 volts per second
respectively).
Summer Feedback
Check that all summers have a 1M ohm resistor connected in
the feedback loop. A single bottle plug may be used for this
purpose, connecting to the input/output positions indicated by
‘1’ (the positions 1 & 10 refer to amplifier gain).
Control Switches and Push Buttons
Check that all rotary switches and push buttons are in the
following positions:
(a) Meter Function Push-button — VM
(b) Mode Control Push-button — IC
(c) Digital Mode Control Push-button — STOP
-(d) Timer switch — 1 second
(e) OP-A and IC-A controls — x1
Slaving Plu
Check that a dummy slaving plug is fitted to the slaving output
socket at the back of the computer. If two computers are to be
slaved together, then a slaving cable should be connected between
the two slaving output sockets.
Switch ON
Switch power ON and allow 10 mihutes warm-up. Note for
safety reasons the power switch is located on the back of the
unit so that no large voltages are connected to the front panel.
Reference Supplies
Check and adjust if necessary both +ve and —ve references
(+1.000 and —1.000 machine units). Reference adjustments are
located at the back of the computer. This is done by connecting
first the positive then the negative reference to the DPM input on
the TRUNK panel.
The Digital Panel Meter should be checked with a 4% digit DVM
approximately every 6 months — no zero adjustment is necessary
and both +ve and —ve fullscale adjustments are performed with
one front panel adjustment (see Maintenance Section).
2.1610
Amplifier Balance
Check amplifier balance by carrying out the following procedure.
a) Set Meter Function Switch to BAL. This operation
automatically operates all amplifier balance relays.
Amplifier output is indicated by the DPM.
b) Select each amplifier in turn and balance if necessary by
inserting a fine pointed srewdriver into the summing
Junction Terminal. The amplifiers may be regarded as
being correctly balanced of the DPM gives a .000+ 1 digit
reading.
c) When complete set Meter Function P/B to AMP.
Digital Panel
If required the clock and mode control operation may be checked
by connecting Cp, R & R to separate lamp indicators. With
Clock Frequency Selector in 1 HZ position, clock operation will
be evident if Digital Mode control P/B are in either RUN or
CLEAR modes. Conditions of R & R signals will change when
Digital mode control P/B is placed in either STOP or RUN modes.
The EAI-180 is now ready for operation.
1 2 3. 4 $ 8
eeeee 6
3° OU 12
7 8
seeese
OVERLOAD INDICATORS j_
oak ‘paleo
a8 sP MO AMP BAL
1 8
AMPLIFIER SELECT
READOUT AND
METER CONTROL
DISPLAY MODE
CONTROL
DIGITAL CONTROL
CONTROL AREAS OF EAI-180 COMPUTER
FIG:2
2.2
ay |; ee
OPERATING INSTRUCTIONS
The EAI-180 Analog/Hybrid small scale computing system, has 3 MAJOR
control areas located on the RH side of the patching area. These are
illustrated in fig. 2 and are —
5 aN
22:2
22:3
READOUT and METER CONTROL
DISPLAY and MODE CONTROL
DIGITAL CONTROL
The function of these control areas will be discussed next. Note that all
push buttons are shown in box fe and sockets in brackets (_ ).
22:1
Readout and Meter Control
This control area allows the selection of amplifier outputs,
meter functions and indicates if any amplifiers exceed limits.
2.2.1.1
METER FUNCTION SWITCH is a 4 position Push-button
switch mounted below the meter and is used to determine
meter functions as set out below.
a) P.B.} When POT BUS position is selected, any
potentiometer setting can be read directly by
depressing the appropriate potentiometer select
switch. This allows quick setting of potentio-
meters to better than + .1%.
b) VM] When the VM position is selected, any
computer or external voltage in the range +20 volts
can be read by applying this voltage to the
(DPM) socket on the TRUNKS panel.
2.2.1.1
221,22
2:2:1..3
tt
c) AMP] This position enables an amplifier output
to be displayed on the output meter by
selecting the appropriate amplifier on the
AMPLIFIER SELECT, 12 position switch.
The selected amplifier output is simultaneously
applied to the (AMP) socket located on the
trunk panel.
d) BAL | The selection of this position actuates all
balancing relays.
AMPLIFIER SELECT SWITCH
This 12 position switch is used to select the amplifier
outputs for presentation to the meter or to the external
readout equipment which has been connected to
(AMP) socket located on the TRUNK panel.
The (AMP) socket is connected directly to the
AMPLIFIER SELECT switch and is not affected by the
position of the METER FUNCTION Switch.
OVERLOAD INDICATORS
When an amplifier output exceeds a voltage of approxi-
mately 10.5 to 11V, the overload INDICATORS will
light and simultaneously ground the overload socket (OVL)
on the TRUNKS panel. The overload light will remain
on until the cause of overload is removed.
2.2.1.4
= 12 -
DIGITAL PANEL METER
This 3% Digit instrument is used to monitor all
computer variables. This unit requires calibration
approximately every 6 months and features a unique
automatic “zeroing” circuit.
NOTE the DPM accuracy is an order higher than the
overall accuracy of the system, hence do not carry out
unnecessary adjustments on the DPM.
22.2
ao co
Display and Mode Control
The Display and Mode Control area shown in fig. 2 provides a
means of controlling the solution of problems set up on the
analog computers and of conveniently connecting these solutions
to display devices.
2.2.2.1 Mode Control
The computer can essentially be placed into 3 modes as
follows —
a) IC
In the initial condition mode, the output voltage
of the integrators are set to the values required
by the initial conditions of the problem.
b) HD
In the hold mode, all inputs to the integrators
are removed and all variables are held at a
“constant value.
c) op
In the operate mode, the integrators accept
inputs and integration and problem solution takes
place.
Integrators can be mode controlled by means of signals
(A) & (A) which may be connected to the integrator
mode control inputs (OP) and (R). The control signals
can assume the values listed in the truth table over leaf.
a fe
MODE A A
Not Allowed 0 0)
Operate OP 0 1
Initial Condition IC ] 0
Hold HD 1 |
Wl
NOTE: 0
1
0 + 0.25 volts (or connected to ground)
3 +1 volt (or open circuit).
There are 4 methods of controlling computer modes and these are
discussed below.
MANUAL OPERATION
In this mode of operation, all integrators connected to the control
busses (A) & (A) can be controlled by using the 3 push buttons
marked JIC}, |HD} and {OP}.
Whenever a push button is: depressed, it will be illuminated to
indicate the mode which has been entered.
REPETITIVE OPERATION _ PP
In this mode an automatic Timer produces repetitive control signals
(A) & (A) which, if connected to the integrator mode controls
(OP) & (R) will repetitively set to IC and OPERATE all integrators
thus connected. The waveforms produced by the Timer are shown
in fig. 3.
The basic Timer period can be adjusted over the ranges shown in
the table below —
TIMER PERIOD OP TIME (A) IC TIME (A)
1 sec 1 sec to 10 sec .1 sec to 1 sec
.1 sec .1 sec to 1 sec .01 sec to .1 sec
10 ms 10 ms to 100 ms 1 ms to 10 ms
1 ms 1 ms to 10 ms .l ms to 1 ms
pa ee
= a ELE
ADJUST OA
PERIOD TIMER oc”
ADJ
OP.
ADJUST OA
| pen ciate S ae
[ic] [HD] [oP] [PP]
FIG: 3 ;
MODE CONTROL & TIMER WAVEFORMS
Pe
The Timer period is controlled by the centrally located 4 position
switch.
The (OP) and (IC) times can be independently adjusted by the
two potentiometer controls over a range of 1:10. The Timer
generator also produces a linear ramp which may be used as a
time base for external display equipment, this is available on the
TRUNKS panel.
Note that during manual operation, the linear ramp will still be
produced when the operate push button is depressed. However,
the ramp output will saturate if the computer is left in the
Operate mode for too long.
SLAVED MODE
TWO EAI-180 Computers can be slaved together to simulate larger
problems. Slaving is carried out by removing the Dummy slaving
plugs and linking the two computers with a slaving cable.
This procedure effectively transfers operation of the mode control
of both computers, to the unit to which the RED coded connector
of the slaving cable is connected.
The mode control of the slave is still operative and may be used
to control integrators by directly patching from the (A) and (A)
sockets on the TRUNKS panel to the individual integrator (OP) |
and (R) sockets.
Amplifier readout selection and metering still remains under the
control of each computer.
EXTERNAL DIGITAL CONTROL
By the connection of appropriate control signals to the OP and R
terminals, the integrator may be controlled by external digital signals.
as a
NOTE: The integrators present approximately one % of a DTL/TTL
unit load and the following input logic levels may be used without
damaging the circuitry,
Logic 1 = + 2.0 volts to + 15 volts or O/C"
Logic 0 = 0 to + 1 volts or S/C.
eae
)
L
fs a arts at al yaar
(|
Ra yt to ato at
2.22.2
_ 5
Trunks and Display Panel
All.-common control signal and display device terminations
are brought out as sockets on the TRUNK panel.
Plotter Inputs (PLOT)
(P) X-Y Plotter pen control.
Depending on the type of X-Y plotter, application of the
appropriate mode control signal (A or A) will ensure pen
is in the UP position when the computer is in the IC mode.
(X) (Y) Plotter inputs, voltages connected to these sockets
will cause the X-Y plotter arm to move.
This socket is also connected to the X input of the CRT
display.
CRT Display scope (DISPLAY)
(Y1)
(Y2) 4 sockets labelled Y1, Y2, Y3, Y4
(Y3) are provided for the connection of
(Y4) 4, Y (vertical) signals to the CRT
display scope.
DIGITAL PANEL METER
(DPM) Provided METER FUNCTION switch is in position
VM, a voltage connected to this socket will be displayed
on the Digital panel meter.
(AMP) Output of AMPLIFIER SELECTOR.
ea |: eee
SYSTEM HOLD
(HLD) Applying a logic zero (short to ground) signal to
this socket will place all integrators into the hold mode.
(OVL) Overload signal generates if an overload condition
exists.
NOTE: If (OVL) is connected to (HDL), the system
“freezes” if an overload occurs.
TRUNKS
(T1) These sockets are connected to a
(T2) connector at the back of the
(T3) computer and are available for trunk-
(T4) ing signals to and from the computer.
( -~|__) Ramp output. This socket provides a ramp
output produced by the system timer. This signal can be used
as an X signal to X-Y recorders or CRT display.
yy SS SP SS ee Be ie le Oe
(JOO HEoe S16 .67 9)
’ an: SY aR: ot |e <A; eee
QQVQIO OOO} QOQQ
. os 3 ¢ eee ae eee
OOO SOOO O6HOA06
, aaah Ay SNS
‘ Oy ea SY S eg it
99 Q9QlOLOO}O 999
FIG: 4
LOGIC CONTROL PATCHING AREA
i =. 2 &. 2 Oe Be SB Se eo, Be Bel
2.2.3
a oe
Digital Control
The following descriptions apply to computers fitted with a digital
panel for basic digital and hybrid problems.
The digital control area is divided into two sections:
a) Operating controls
b) Control patching area
Note that the operating control outputs are available on the control
patching area.
The digital control area is further sub-divided into 4 functional
areas which are clearly shown in fig. 4.
A block diagram of the complete digital control circuitry is shown
in fig. 5.
These separate control areas will be discussed next.
Note, all control area inputs represent a single DTL load and all
outputs will drive 20 DTL loads.
2.2.3.1 DIGITAL MODE CONTROL
The clocked logic section of the digital panel is supplied
with control busses:
a) Clock Bus
b) Counter Reset Bus
c) Flip Flop Reset Bus
to which a clock source and reset signals should be
applied. In normal operation a double bottle plug would
be inserted to join (R) to counter Reset Bus (C), (R) to
(FF) reset bus and a single bottle plug from (Cp) source
to the CLOCK bus.
©) cp©
CLOCK BUS
CLOCK SPEED
© 7© |
ee eo ee
| GENERATOR }——o
Fall ——_°
olay
E© :
= © ie 6!
RUN STOP | CLEAR
COUNTER
reser OC R©
FLIP FLOP © oa
RESET sale
BLOCK DIAGRAM OF DIGITAL CONTROL
= SF ie. &
nee ee ee ee ee ne ee ol
fine
22:3:2
ie) ae
Any logic which is then connected to these busses can
be controlled by operating the 3 mode control push
button switches.
The mode control switches have the following functions —
a) [RUN | Clock pulses are applied to CP bus.
b) |STOP]} Clock pulses are disabled
c) |CLEAR] Reset Busses are activated.
As an alternative to the above manual operation, mode
control can be performed by external logic control of
these functions.
For this purpose two control gates are provided:
a) (STOP) gate; a two input gate which stops clock
operation if either of the inputs is taken to logic 0.
b) (RESET) gate; a two input gate which operates the
reset busses if either input is taken to logic 0.
CLOCK SOURCE
A Clock source is provided which supplies frquencies from
1 HZ to 10 KHZ in decade increments. The frequency
accuracy is approximately 5%. If a precise frequency is
required, this may be obtained by using an external
capacitor mounted at the terminals provided in the control
patching area.
NOTE: The clock frequency can only be reduced by the
addition of an external capacitor.
el
Sl
hn tee tet tg
OE
2.2.3.4
— 4 —
The clock source also provides a pulse output (P) and
(P) which occurs whenever the clock changes level.
The appropriate ‘waveforms are shown in fig. 5.
NOTE: Only a single bottle plug should be used in
connecting clock source to CLOCK Bus.
SWITCHES
Eight independent control switches are provided on the
control panel.
These switches operate switch bounce elimination bistables
whose outputs (S) and (S) are made available on the
control patching area.
The switches operate according to the following truth
_ table.
Switch Setting (S) Output (S) Output
0 Logic 0 Logic 1
1 Logic, = Logic 0
(1) Momentary Momentary
logic 1 logic 0
These switches may be used to operate logic in single
shot mode, set binary values, etc.
INDICATORS
Eight gated independent lamps are provided to display
the states of the logic variables.
Each lamp is driven by a 2 input AND gate. An un-
connected terminal will act as if a logic 1 were presented
at its input.
CHAPTER 3
COMPONENT DESCRIPTION
The active components of the EAI 180 are located on 3 panels —
(A) LINEAR PANEL
(B) NON LINEAR PANEL
(C) DIGITAL PANEL
3.1 LINEAR PANEL
The Linear panel as illustrated in fig. 6 contains the patching outlets for
up to —
6 Integrators
3 Dual Summers.
The Procedures for balancing these amplifiers has been outlined in
Chapter 1 and their characteristics will next be described.
3.1.1 Dual Summers
Both the front panel layout and schematic diagram of the Dual
Summer is shown in fig. 7.
Each Summer consists of a high performance Fet-input operational
amplifier and 5 computing resistors.
a) Three 1 M ohm Resistors (Gain 1)
b) Two 100K ohm Resistors (Gain 10).
These precision resistors are matched to 0.25%.
In operating the Summer an appropriate feedback resistor should
always be connected otherwise an overload condition will result.
The computing resistors may be arranged in any gain configuration
between .1 and 10. GAIN values outside these limits may result
in some degradation of performance.
Lu
tl gn ator aren a
nos! a!
ae ee
FA180
vm AMP gat
or
OVERLOAD INDICATORS
AMPLIFIER SELECT
AMPLIFIER PANEL. LAYOUT
FIG; 6
oa 7 ee
AMPLIFIER
SUMMING
JUNCTION
1 O) (top only)
DUAL SUMMER
180-22
—
‘3 ADJUST
a _
—
oO
=> —_- —
“=
Oo
eee anes:
022 O ALE 9 Ok
=
oO
FIG:7
DUAL SUMMER BLOCK DIAGRAM
AND FRONT PANEL
a a re pre ars ar ae pare aa aa
lt
L
a a
SUMMER PATCHING CONFIGUATIONS
INVERTER
-X/10
—10X
FIG:8aq
7
x 4
—(X+Y)
Y 4
x6 ©)
YO-—-vyvwws—4 © Y
4 “4 =( X4¥+Z)/10
Soa Se
Eww —_—« O&O —
=-K(X+10Y)
K
SUMMER PATCHING CONFIGUATIONS
FIG: 8b
— Ll Md) Mell) lm) shh le
ae | oe
The maximum output current capability of the operational amplifiers
used is + 5 MA; the amplifier is short circuit proof to ground or
either reference supplies.
This output current rating places a limit on the number of potentio-
meters which may be driven.
Patching configurations — Figs. 8a and 8b show some of the
patching configuration which can be used with the summer.
Integrators
The front Panel layout and schematic diagram of the integrator is
shown in fig. 9.
Each integrator consists of a Fet input operational amplifier,
electronic mode control switches and the following computing
components.
a) Two 1M ohm resistors (Gain 1)
b) Two 100K ohm resistors (Gain 10)
c) One 10K ohm initial condition input (Gain 1)
d) One 1 micro farad capacitor (Gain 1)
e) One .01 micro farad capacitor (Gain 100).
The resistors are matched to within .25% and the capacitors are
accurate within 25%.
An appropriate feedback component should always be connected
otherwise an overload condition will result. It is also advisable to
connect the integrator mode control inputs to the mode control
signals (A) and (A) by using a double shorting plug.
NOTE that if mode control inputs (OP) and (R) are open
circuited then integrator will be in HOLD mode.
10K 10K
cO Bae : ak
meas yeas
oa 1M
‘© ——-
Summing |
‘O—wn.+4 Junction Amplifier
100K
0 O—ww—-4
100K
: : OP INTEGRATOR
180-21
opC) Oa
ae Oa
BALANCE ADJUSTMENT
1
FUNCTION 1OMROY
F
OP | R
0 o | NOT ALLOWED 10m, OF
0 1 COMPUTE 10 Ow
1 QO | INITIAL CONDITION °
1 1 | HOLD 10Oww On
SJ
1
t
tO|Q O
ie)
FIG:9
INTEGRATOR BLOCK DIAGRAM
AND FRONT PANEL LAYOUT
oo at an aw
Sg ag a ar aes mare ao ato arene eho aren
ae
SS ae
©--—---—-—-— ~~ ©)
oO Mee Te ee ve) Y
X4 6 ©
Xy-O-VWw—4 x, Lf
~yO-wwnv—-4 © Xe : Z
XxO-vwwse—4 © — ‘ 10
Onn —+ O41
YO Z=-[ Yoh" X+ Xs10Xs 10X) dé]
INTEGRATOR
©” ‘6
Contrelieye . 6
O-VWws—-+——_© 3
oO RUA CRA Xe Y
62 ee ee ©
©2 pe ge RO © Control
Sample =0
Ox wo! GCiw Hold =1
oO O41
Xe —©) Ic
SAMPLE & HOLD
INTEGRATOR PATCHING
(H-Or QO =o
‘Ob-wwwwse—+s—_O | >—
iO WO [ ie
nelworl 10 =
O-WwWws—-4 ©) :
Om oywwy © T -----— —o-~
@ut ° ©CHke
O- O4WH
x —O)Ic ©—)
X caf
epee network
INTEGRATOR PATCHED AS INVERTER/FREE NETWORK
INTEGRATOR PATCHING
FIG:lOb
Fe
eS
The computing components may be arranged to give gains of
1 Volt/Sec to 1,000 Volt/Sec. Gain values outside these limits
may result in significant degradation of performance.
The integrator may be operated in a number of modes by using
the elctronic switches in a different configuration.
The integrator may be operated in the configurations shown in
fig’s 10a and 10b.
NON LINEAR PANEL
The Non Linear panel as illustrated in fig. 11 contains the patching outlets
for the following components:
a) Reference Supplies
b) Potentiometers
c) Function Relays
d) Comparators
e) Multipliers
f) DFG’s
g) Function Board (optional) — Sin/Cos, Log/Antilog, Vector,
Free Function
NOTE: These components are not provided with any special monitoring or
overload indication features.
The above components will next be described in detail.
3.2.1 Reference & Potentiometer Panel
Six of these panels are located in the non-linear panel and each
contains the following: —
a) +10.00 Volt and —10.00 Volt reference outlets
b) One single ended 10K potentiometer
c) One double ended 10K potentiometer.
The schematic diagram and panel layout is shown in fig. 12.
—. 85: =
NON LINEAR PANEL LAYOUT
1
P VG.
Ll
a i am aan aa ay (aaa ‘aay (RY aa) PR jas THPPP ay TY sas TOP aay TI Aly VOR jy YI way I yt ae
_ Ge.
REF &POTS
180-21
@
@
e)
d
FIG:l2
REFERENCE & POT PANEL
3.2.2
S225
aby: § Stee
Function Relays
This unit contains 4 independent Function relays whose schematic
is shown in fig. 13.
These change over switches can be operated by logic signals
derived from —
a) Control signals (A) and (A)
b) Comparator logic outputs
c) Logic signals
Electronic Comparator Panel
This unit contains four independent electronic comparators whose
front panel layouts and schematic is shown in fig. 14.
The function of these units is to provide a means of comparing
two analog voltages E; & E> and produce a logic output which
indicates whether
E, + Ex<x 0
or £1, +E, >>0
In operation the voltages E,; and E> are applied through ‘100K input’
resistors to the SJ input of a High gain Op amp. If the voltage on
the SJ input is positive, then a logic 1 appears on the T output.
If this voltage is negative, then a logic O appears on T output.
This is shown in the truth table on page 40.
eal head
a
hemes
eu!” am” oma” ae)!” Ml A” A
= a pe!
I
= 32
FUNCTION RELAYS
180 - 36
a0 | [4
ae
aot
pate:
en
ML
Lee me,
FUNCTION RELAYS
FIG:I3
Se
‘@hi
E2 © |
COMPARATOR i
INVERTER
COMPARATORS
180-350
+10
=
oO
2 212 P/E QIO O
(| Siskekbc
FIG: 14
COMPARATOR FRONT PANEL LAYOUT
AND BLOCK DIAGRAM
~_— # }
ae: we
Conditions at Inputs }| Output
E, + E> = positive T= t@
E, + E> = negative Oe a
NOTE: Logic 1
Logic 0
5V
OV
T & T are capable of driving 5 DTL loads. The comparator out-
put may be used to control integrator modes or logic circuits.
The outputs of the comparators may be connected (‘wired OR’)
together to produce multiple comparisons.
3.2.4 Multiplier Panel
Each multiplier position can be fitted with either one, two, three
or four Multipliers. A block diagram and front panel layout is
shown in fig. 15.
The multiplier used is of the transconductance type which produces
a product of XY in all four quadrants from inputs X and Y.
10
No external amplifiers are required to perform multiplication,
squaring, division or square root operation.
Fig. 16 shows the various multiplier configurations required to
perform the different operations.
The multiplier has an accuracy of 1% in all quadrants.
There is one adjustment available on the patch panel see fig. 15,
which is —
Se eee
MULTIPLIER
180 -331
-10
OO
ono
MI
M2
OFFSET
ADJUSTMENT
Sap gS 22
FIG: [5
MULTIPLIER FRONT PANEL LAYOUT
ma Gel el tad ed
—
ee ee
*\ me
SADE
eel] — [xt a ee
Y yO LO— XY/10 yO -O- X10
MULTIPLICATION SQUARING
ns Oe O, ia O:
ew as
| io ay LO — 102/x Y Qu :
DIVIDING SQUARE ROOTING
MULTIPLIER CONFIGUATIONS
FIG: 16
B25
Lag
Output offset (Null output for zero input)
Internally two other adjustments are available namely —
X Feedthrough
Y Feedthrough
however, these two adjustements have been made in the factory
for optimum 4 Quadrant operation and no adjustment should be
attempted without reference to maintenance section.
Diode Function Generator
This unit is a fixed breakpoint, variable slope DFG. There are 4 sets
of break points located at + 2 volts, + 4 volts, + 6V and +8V
together with a central slope adjustment. The front panel layout and
block diagram is shown in fig. 17. Hence if a symmetrical non linearity
has to be generated then the unit has effectively 10 segments.
The easiest way to observe this DFG is to use a ramp input, generated
by an integrator, which varies from +10 to —10 volts.
With the above voltage applied to the DFG input, monitor the output
on an oscilloscope and perform the following patching and set up
operations.
a) Adjust Parallax pot to give required output Y level
at Vin = 0.
b) Connect CS to either + slope or — slope to produce
+ ve. or — ve central initial slope.
Use CS ADJ for desired central slope.
c) Connect $1 to either + or — slope to produce a + ve
or — ve slope at 2V point with respect to the central
slope.
d) Connect $2 to either + or — slope as above to produce
next slope at 4V point.
)p
CS Vs=2V
| =a
) |
-10 S1 Vs =|4V
INPUT ©
TEST p SSS ~
WAV EFORM eo Vs =!6V
|
) |
: VOLTAGE
SENSITIVE
SW.
PARALLAX
Di FG
180-340
C) PARALLAX
Oa)
FIG: 17
DFG FRONT PANEL LAYOUT &
BLOCK DIAGRAM
3.2.6
aie ee
e) Connect $3 and $4 to + or slope to produce last
2 slopes at 6V and 8V.
f) Procedure (c) to (e) should be repeated if required.
Theory of Operation
With zero volts in, the output of the DFG is set by the parallax
control which applies an offset voltage on the output.
As the input voltage increases between 0 and + 2V, a linear output
is produced whose slope is determined by the Central slope adjust-
ment, the polarity of the output slope being determined by whether
the input current is applied to Al or A2 input.
When the voltage exceeds + 2V, the output at the + 2V breakpoint
has slope determined by the S1 adjustment, polarity again determined
by the connection to Al or A2.
As the input voltage increases further, breakpoints at 4V, 6V and
8V operate in succession, each contributing current to Al or A2
amplifier hence altering the slope of the output voltage at each
breakpoint.
A typical output waveshape for the patching of fig. 17, can be
observed in fig. 18.
Optional Function Generators
Sin/Cos Function Generator
Log/Antilog Function Generator
Vector Function Generator
UN w >
Free Function Generator
pate | ee
“VOUT
A
10 =
IFRS83
s So S4
6 oa
[/
4
+CS
7, a
yaaa
_ BV'IN
=10- - <8" :=6> =-4 2 2 4 6 8 10
2
4
6
8
10
v
FIG:I8 TYPICAL OUTPUT
of +5 SEGMENT DFG
ae = Oe
A. _Sin/Cos Function Generator
This unit is an analog function module that may be connected to
provide various trigonometric gain responses. It provides a D.C.
voltage output proportional to the sine of an input voltage where
+ 10 Volts of input voltage represents + 90 degrees of input angle.
In addition, the module may be connected to form cosine functions.
Transfer equations are: —
(i) For Sine Function, Eo = —10 sin 0 where @ = 9E, degrees
and —10V<= E, == +10V.
(ii) For Cosine function, Eo = 10 cos 8 where @ = 9E, degrees
and Os Ey<+10 (for Ey = —10V) and OSE ;==—-10
(for Ey = +10V),
Accuracy can be expected to be + 1% from D.C. to 1KHZ.
Output offset has been adjusted at the factory for optimum
performance.
Fig. 19 shows the output functions for sine and cosine operation.
Fig. 20 indicates the patching procedure.
B. _Log/Antilog function Generator
This unit will provide computation of the log or antilog of a
negative input voltage or the log of a negative input current.
Transfer equations are: —
Ein — Eos
(i) For Log mode, E out = —K log 10 ( Eref
: —Ein
(ii) For Antilog mode, E out = Iref.Rf. 10K + Eos.
= AR
+10Vt
T+5SV
-10V -5V *5Vs10V_
-5SVtr
-10VtT
SINE FUNCTION
+10 Ve
E5=+10V
x 2
~10V :
COSINE FUNCTION
FIG. 19
wx) AB cs
IN FOR SINE/COSINE
+REF OR -—REF FOR
COSINE, O/C FOR SINE
PATCHING DIAGRAM FOR SINE/COSINE GENERATOR
O75 ©) ~
BINcoshy | output
OHE2 IO]
FIG: 20
X_ INPUT
Y INPUT
X
VECTOR
On
PATCHING DIAGRAM FOR VECTOR GENERATOR
¥
\Heo/
[> ouTPut [x74 Y?
FIG: 21
_,
2 =
Input Ranges
Ein = lin X Rin,
where lin = —100 pA to —1 mA and Rin = 10K ohms
2c Eine.
Sora
E ref @ R in X | ref for Rin = 10K ohms
Decades of input current available, for + 10V output
are defined by + decades input current = oe
NOTE:
Amplifier offset (Eos) has been adjusted at the factory. However,
for ultimate accuracy, offsets should be checked and adjusted if
necessary, so eliminating Eos from the transfer equations.
External Operational Adjustments
Log Mode
li Check offset conditions
Connect as per Fig. 22
Insert an input current equal to the desired reference current,
and adjust R2 for Eo = OV.
4. Increase the input current by a factor of 10, and adjust R1
for + k volts at the output
5: Repeat steps 3 and 4
Antilog Mode
Check offset conditions
Connect as per Fig. 23
Set E in to OV and adjust R2 for Eo=I ret X Rf
where | ref = desired reference current.
4. Set E in to —K (K = desired scale factor) and adjust R1
for an output volta